FR2182799B2 - - Google Patents
Info
- Publication number
- FR2182799B2 FR2182799B2 FR7246923A FR7246923A FR2182799B2 FR 2182799 B2 FR2182799 B2 FR 2182799B2 FR 7246923 A FR7246923 A FR 7246923A FR 7246923 A FR7246923 A FR 7246923A FR 2182799 B2 FR2182799 B2 FR 2182799B2
- Authority
- FR
- France
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1407—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
- G11B20/1419—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19722221455 DE2221455C3 (en) | 1972-05-02 | 1972-05-02 | Circuit arrangement for generating clock pulses |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR2182799A2 FR2182799A2 (en) | 1973-12-14 |
| FR2182799B2 true FR2182799B2 (en) | 1978-05-26 |
Family
ID=5843846
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR7246923A Expired FR2182799B2 (en) | 1972-05-02 | 1972-12-29 |
Country Status (5)
| Country | Link |
|---|---|
| BE (1) | BE799004R (en) |
| DE (1) | DE2221455C3 (en) |
| FR (1) | FR2182799B2 (en) |
| GB (1) | GB1406924A (en) |
| IT (1) | IT1035602B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2906200C3 (en) * | 1979-02-17 | 1982-02-11 | Philips Patentverwaltung Gmbh, 2000 Hamburg | Synchronizing arrangement |
| JPS5720052A (en) | 1980-07-11 | 1982-02-02 | Toshiba Corp | Input data synchronizing circuit |
| DE3202945C2 (en) * | 1982-01-29 | 1985-12-05 | Siemens AG, 1000 Berlin und 8000 München | Method and arrangement for generating window pulses (data and possibly clock window pulses) for a separator circuit for separating the data pulses from accompanying pulses when reading magnetic tape or disk memories, in particular floppy disk memories |
-
1972
- 1972-05-02 DE DE19722221455 patent/DE2221455C3/en not_active Expired
- 1972-12-29 FR FR7246923A patent/FR2182799B2/fr not_active Expired
-
1973
- 1973-04-27 IT IT2348573A patent/IT1035602B/en active
- 1973-05-01 GB GB2062373A patent/GB1406924A/en not_active Expired
- 1973-05-02 BE BE130666A patent/BE799004R/en active
Also Published As
| Publication number | Publication date |
|---|---|
| IT1035602B (en) | 1979-10-20 |
| BE799004R (en) | 1973-11-05 |
| GB1406924A (en) | 1975-09-17 |
| FR2182799A2 (en) | 1973-12-14 |
| DE2221455B2 (en) | 1974-09-12 |
| DE2221455C3 (en) | 1975-06-19 |
| DE2221455A1 (en) | 1973-11-15 |