FR2172242A1 - - Google Patents
Info
- Publication number
- FR2172242A1 FR2172242A1 FR7305222A FR7305222A FR2172242A1 FR 2172242 A1 FR2172242 A1 FR 2172242A1 FR 7305222 A FR7305222 A FR 7305222A FR 7305222 A FR7305222 A FR 7305222A FR 2172242 A1 FR2172242 A1 FR 2172242A1
- Authority
- FR
- France
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
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- H10P95/00—
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
- H01L23/4822—Beam leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA134841 | 1972-02-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| FR2172242A1 true FR2172242A1 (en:Method) | 1973-09-28 |
Family
ID=4092355
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR7305222A Withdrawn FR2172242A1 (en:Method) | 1972-02-16 | 1973-02-14 |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS4895180A (en:Method) |
| CA (1) | CA929675A (en:Method) |
| DE (1) | DE2307021A1 (en:Method) |
| FR (1) | FR2172242A1 (en:Method) |
| NL (1) | NL7215385A (en:Method) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2388064A1 (fr) * | 1977-04-18 | 1978-11-17 | Philips Nv | Procede pour renforcer par voie galvanique un motif de base conducteur et dispositif obtenu suivant ce procede |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL7605233A (nl) * | 1976-05-17 | 1977-11-21 | Philips Nv | Van een micro circuit voorziene elementaire schijf met electrolytisch aangegroeide soldeerbollen alsmede werkwijze voor het vervaardigen daarvan. |
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1972
- 1972-02-16 CA CA929675A patent/CA929675A/en not_active Expired
- 1972-11-09 JP JP47111698A patent/JPS4895180A/ja active Pending
- 1972-11-14 NL NL7215385A patent/NL7215385A/xx unknown
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1973
- 1973-02-13 DE DE2307021A patent/DE2307021A1/de active Pending
- 1973-02-14 FR FR7305222A patent/FR2172242A1/fr not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2388064A1 (fr) * | 1977-04-18 | 1978-11-17 | Philips Nv | Procede pour renforcer par voie galvanique un motif de base conducteur et dispositif obtenu suivant ce procede |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS4895180A (en:Method) | 1973-12-06 |
| DE2307021A1 (de) | 1973-09-13 |
| NL7215385A (en:Method) | 1973-08-20 |
| CA929675A (en) | 1973-07-03 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| ST | Notification of lapse |