FR2152719A1 - - Google Patents

Info

Publication number
FR2152719A1
FR2152719A1 FR7231721A FR7231721A FR2152719A1 FR 2152719 A1 FR2152719 A1 FR 2152719A1 FR 7231721 A FR7231721 A FR 7231721A FR 7231721 A FR7231721 A FR 7231721A FR 2152719 A1 FR2152719 A1 FR 2152719A1
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR7231721A
Other languages
French (fr)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zentronik VEB
Original Assignee
Zentronik VEB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zentronik VEB filed Critical Zentronik VEB
Publication of FR2152719A1 publication Critical patent/FR2152719A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
    • G06F5/085—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register in which the data is recirculated
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
FR7231721A 1971-09-08 1972-09-07 Withdrawn FR2152719A1 (enExample)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DD15761071 1971-09-08

Publications (1)

Publication Number Publication Date
FR2152719A1 true FR2152719A1 (enExample) 1973-04-27

Family

ID=5484304

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7231721A Withdrawn FR2152719A1 (enExample) 1971-09-08 1972-09-07

Country Status (3)

Country Link
CS (1) CS162479B1 (enExample)
DE (1) DE2237928A1 (enExample)
FR (1) FR2152719A1 (enExample)

Also Published As

Publication number Publication date
DE2237928A1 (de) 1973-03-15
CS162479B1 (enExample) 1975-07-15

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Legal Events

Date Code Title Description
ST Notification of lapse