FR2148439A1 - - Google Patents

Info

Publication number
FR2148439A1
FR2148439A1 FR7227021A FR7227021A FR2148439A1 FR 2148439 A1 FR2148439 A1 FR 2148439A1 FR 7227021 A FR7227021 A FR 7227021A FR 7227021 A FR7227021 A FR 7227021A FR 2148439 A1 FR2148439 A1 FR 2148439A1
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7227021A
Other languages
French (fr)
Other versions
FR2148439B1 (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Micronas GmbH
ITT Inc
Original Assignee
Deutsche ITT Industries GmbH
ITT Industries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche ITT Industries GmbH, ITT Industries Inc filed Critical Deutsche ITT Industries GmbH
Publication of FR2148439A1 publication Critical patent/FR2148439A1/fr
Application granted granted Critical
Publication of FR2148439B1 publication Critical patent/FR2148439B1/fr
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor

Landscapes

  • Microelectronics & Electronic Packaging (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Weting (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
FR7227021A 1971-08-07 1972-07-27 Expired FR2148439B1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2139631A DE2139631C3 (en) 1971-08-07 1971-08-07 Method for producing a semiconductor component, in which the edge of a diffusion zone is aligned with the edge of a polycrystalline silicon electrode

Publications (2)

Publication Number Publication Date
FR2148439A1 true FR2148439A1 (en) 1973-03-23
FR2148439B1 FR2148439B1 (en) 1976-03-12

Family

ID=5816091

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7227021A Expired FR2148439B1 (en) 1971-08-07 1972-07-27

Country Status (7)

Country Link
JP (1) JPS4829370A (en)
AU (1) AU4513372A (en)
DE (1) DE2139631C3 (en)
FR (1) FR2148439B1 (en)
GB (1) GB1339384A (en)
IT (1) IT963314B (en)
ZA (1) ZA724729B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2330146A1 (en) * 1975-10-29 1977-05-27 Intel Corp AUTOMATIC ALIGNMENT ENGRAVING PROCESS OF A DOUBLE LAYER OF POLYCRYSTALLINE SILICON

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5131255B1 (en) * 1971-02-27 1976-09-06
JPS56130497A (en) * 1980-03-19 1981-10-13 Toyota Motor Corp Formation of pattern or the like utilizing electro-deposition coating
US4318759A (en) * 1980-07-21 1982-03-09 Data General Corporation Retro-etch process for integrated circuits
JPS6137998A (en) * 1984-07-27 1986-02-22 Seiko Instr & Electronics Ltd Manufacture of dial of timepiece

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2330146A1 (en) * 1975-10-29 1977-05-27 Intel Corp AUTOMATIC ALIGNMENT ENGRAVING PROCESS OF A DOUBLE LAYER OF POLYCRYSTALLINE SILICON

Also Published As

Publication number Publication date
DE2139631B2 (en) 1978-08-31
DE2139631C3 (en) 1979-05-10
FR2148439B1 (en) 1976-03-12
AU4513372A (en) 1974-02-07
IT963314B (en) 1974-01-10
JPS4829370A (en) 1973-04-18
ZA724729B (en) 1973-04-25
GB1339384A (en) 1973-12-05
DE2139631A1 (en) 1973-03-01

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Legal Events

Date Code Title Description
ST Notification of lapse