FR2133156A5 - - Google Patents

Info

Publication number
FR2133156A5
FR2133156A5 FR7112645A FR7112645A FR2133156A5 FR 2133156 A5 FR2133156 A5 FR 2133156A5 FR 7112645 A FR7112645 A FR 7112645A FR 7112645 A FR7112645 A FR 7112645A FR 2133156 A5 FR2133156 A5 FR 2133156A5
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR7112645A
Other languages
French (fr)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
INFORMATIQUE CIE INTERNA
Original Assignee
INFORMATIQUE CIE INTERNA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by INFORMATIQUE CIE INTERNA filed Critical INFORMATIQUE CIE INTERNA
Priority to FR7112645A priority Critical patent/FR2133156A5/fr
Application granted granted Critical
Publication of FR2133156A5 publication Critical patent/FR2133156A5/fr
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0353—Making conductive layer thin, e.g. by etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
FR7112645A 1971-04-09 1971-04-09 Expired FR2133156A5 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR7112645A FR2133156A5 (ja) 1971-04-09 1971-04-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7112645A FR2133156A5 (ja) 1971-04-09 1971-04-09

Publications (1)

Publication Number Publication Date
FR2133156A5 true FR2133156A5 (ja) 1972-11-24

Family

ID=9075059

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7112645A Expired FR2133156A5 (ja) 1971-04-09 1971-04-09

Country Status (1)

Country Link
FR (1) FR2133156A5 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2650471A1 (fr) * 1989-07-27 1991-02-01 Bull Sa Procede de formation de piliers du reseau multicouche d'une carte de connexion d'au moins un circuit integre de haute densite
US5082718A (en) * 1989-07-27 1992-01-21 Bull S.A. Method for depositing an insulating layer on a conductive layer of a multi-layer connection board of one very large scale integrated circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2650471A1 (fr) * 1989-07-27 1991-02-01 Bull Sa Procede de formation de piliers du reseau multicouche d'une carte de connexion d'au moins un circuit integre de haute densite
EP0411985A1 (fr) * 1989-07-27 1991-02-06 Bull S.A. Procédé de formation du réseau multicouche d'une carte de connexion d'au moins un circuit intégré de haute densité
US5082718A (en) * 1989-07-27 1992-01-21 Bull S.A. Method for depositing an insulating layer on a conductive layer of a multi-layer connection board of one very large scale integrated circuit
US5231757A (en) * 1989-07-27 1993-08-03 Bull, S.A. Method for forming the multi-layer structure of a connection board of at least one very large scale integrated circuit

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Legal Events

Date Code Title Description
CD Change of name or company name
TP Transmission of property
ST Notification of lapse