FR2108201A1 - - Google Patents
Info
- Publication number
- FR2108201A1 FR2108201A1 FR7129542A FR7129542A FR2108201A1 FR 2108201 A1 FR2108201 A1 FR 2108201A1 FR 7129542 A FR7129542 A FR 7129542A FR 7129542 A FR7129542 A FR 7129542A FR 2108201 A1 FR2108201 A1 FR 2108201A1
- Authority
- FR
- France
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
- G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
- G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US6382470A | 1970-08-14 | 1970-08-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| FR2108201A1 true FR2108201A1 (ref) | 1972-05-19 |
Family
ID=22051753
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR7129542A Withdrawn FR2108201A1 (ref) | 1970-08-14 | 1971-08-12 |
Country Status (3)
| Country | Link |
|---|---|
| DE (1) | DE2140426A1 (ref) |
| FR (1) | FR2108201A1 (ref) |
| NL (1) | NL7110918A (ref) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0052617A4 (en) * | 1980-05-29 | 1984-10-25 | Motorola Inc | MEMORY NETWORK HAVING IMPROVED INSULATION BETWEEN THE READING LINES. |
-
1971
- 1971-08-06 NL NL7110918A patent/NL7110918A/xx unknown
- 1971-08-12 DE DE19712140426 patent/DE2140426A1/de active Pending
- 1971-08-12 FR FR7129542A patent/FR2108201A1/fr not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0052617A4 (en) * | 1980-05-29 | 1984-10-25 | Motorola Inc | MEMORY NETWORK HAVING IMPROVED INSULATION BETWEEN THE READING LINES. |
Also Published As
| Publication number | Publication date |
|---|---|
| NL7110918A (ref) | 1972-02-16 |
| DE2140426A1 (de) | 1972-02-17 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| ST | Notification of lapse |