FR2105704A5 - - Google Patents

Info

Publication number
FR2105704A5
FR2105704A5 FR7033736A FR7033736A FR2105704A5 FR 2105704 A5 FR2105704 A5 FR 2105704A5 FR 7033736 A FR7033736 A FR 7033736A FR 7033736 A FR7033736 A FR 7033736A FR 2105704 A5 FR2105704 A5 FR 2105704A5
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR7033736A
Other languages
French (fr)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thomson CSF SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson CSF SA filed Critical Thomson CSF SA
Priority to FR7033736A priority Critical patent/FR2105704A5/fr
Application granted granted Critical
Publication of FR2105704A5 publication Critical patent/FR2105704A5/fr
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G06F7/575Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096Synchronous circuits, i.e. using clock signals
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804Details
    • G06F2207/386Special constructional features
    • G06F2207/3872Precharge of output to prevent leakage

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • Computational Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
FR7033736A 1970-09-17 1970-09-17 Expired FR2105704A5 (nl)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR7033736A FR2105704A5 (nl) 1970-09-17 1970-09-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7033736A FR2105704A5 (nl) 1970-09-17 1970-09-17

Publications (1)

Publication Number Publication Date
FR2105704A5 true FR2105704A5 (nl) 1972-04-28

Family

ID=9061448

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7033736A Expired FR2105704A5 (nl) 1970-09-17 1970-09-17

Country Status (1)

Country Link
FR (1) FR2105704A5 (nl)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0101123A1 (en) * 1982-08-10 1984-02-22 Koninklijke Philips Electronics N.V. Integrated logic circuit incorporating fast sample control

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0101123A1 (en) * 1982-08-10 1984-02-22 Koninklijke Philips Electronics N.V. Integrated logic circuit incorporating fast sample control

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Legal Events

Date Code Title Description
ST Notification of lapse