FR2080824B1 - - Google Patents
Info
- Publication number
- FR2080824B1 FR2080824B1 FR7106649A FR7106649A FR2080824B1 FR 2080824 B1 FR2080824 B1 FR 2080824B1 FR 7106649 A FR7106649 A FR 7106649A FR 7106649 A FR7106649 A FR 7106649A FR 2080824 B1 FR2080824 B1 FR 2080824B1
- Authority
- FR
- France
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318502—Test of Combinational circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/02—Comparing digital values
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/26—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to difference between voltages or between currents; responsive to phase angle between voltages or between currents
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Nonlinear Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Manipulation Of Pulses (AREA)
- Safety Devices In Control Systems (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19702009565 DE2009565A1 (de) | 1970-02-28 | 1970-02-28 | Fehlergeschützte Vergleichseinrichtung für analoge und binäre elektrische Signale |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2080824A1 FR2080824A1 (de) | 1971-11-19 |
FR2080824B1 true FR2080824B1 (de) | 1977-03-18 |
Family
ID=5763719
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7106649A Expired FR2080824B1 (de) | 1970-02-28 | 1971-02-26 |
Country Status (7)
Country | Link |
---|---|
AT (1) | AT311093B (de) |
CH (1) | CH518036A (de) |
DE (1) | DE2009565A1 (de) |
FR (1) | FR2080824B1 (de) |
GB (1) | GB1302489A (de) |
NL (1) | NL7102558A (de) |
NO (1) | NO129594B (de) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2536922A1 (fr) * | 1982-11-26 | 1984-06-01 | Efcis | Comparateur logique a plusieurs fonctions |
JP4141039B2 (ja) * | 1998-06-10 | 2008-08-27 | 日本信号株式会社 | 閾値演算回路及びこれを用いたandゲート回路、自己保持回路及び起動信号発生回路 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3492589A (en) * | 1967-04-03 | 1970-01-27 | Honeywell Inc | Failsafe circuit apparatus |
FR1567305A (fr) * | 1967-04-03 | 1968-05-16 | Honeywell Inc | Procédé et dispositif pour la comparaison des grandeurs de deux signaux continus et d'un signal altenatif. |
-
1970
- 1970-02-28 DE DE19702009565 patent/DE2009565A1/de active Pending
-
1971
- 1971-02-05 CH CH169771A patent/CH518036A/de not_active IP Right Cessation
- 1971-02-09 AT AT106071A patent/AT311093B/de not_active IP Right Cessation
- 1971-02-26 NO NO00729/71A patent/NO129594B/no unknown
- 1971-02-26 NL NL7102558A patent/NL7102558A/xx unknown
- 1971-02-26 FR FR7106649A patent/FR2080824B1/fr not_active Expired
- 1971-04-19 GB GB2431571*A patent/GB1302489A/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
AT311093B (de) | 1973-10-25 |
NO129594B (de) | 1974-04-29 |
CH518036A (de) | 1972-01-15 |
GB1302489A (de) | 1973-01-10 |
FR2080824A1 (de) | 1971-11-19 |
NL7102558A (de) | 1971-08-31 |
DE2009565A1 (de) | 1971-09-09 |
Similar Documents
Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |