FR2050087A5 - - Google Patents

Info

Publication number
FR2050087A5
FR2050087A5 FR7020942A FR7020942A FR2050087A5 FR 2050087 A5 FR2050087 A5 FR 2050087A5 FR 7020942 A FR7020942 A FR 7020942A FR 7020942 A FR7020942 A FR 7020942A FR 2050087 A5 FR2050087 A5 FR 2050087A5
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR7020942A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Application granted granted Critical
Publication of FR2050087A5 publication Critical patent/FR2050087A5/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/509—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators
    • G06F7/5095—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators word-serial, i.e. with an accumulator-register

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Error Detection And Correction (AREA)
FR7020942A 1969-06-07 1970-06-08 Expired FR2050087A5 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL6908710A NL6908710A (fr) 1969-06-07 1969-06-07

Publications (1)

Publication Number Publication Date
FR2050087A5 true FR2050087A5 (fr) 1971-03-26

Family

ID=19807130

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7020942A Expired FR2050087A5 (fr) 1969-06-07 1970-06-08

Country Status (5)

Country Link
US (1) US3676657A (fr)
DE (1) DE2025079A1 (fr)
FR (1) FR2050087A5 (fr)
GB (1) GB1313169A (fr)
NL (1) NL6908710A (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4707800A (en) * 1985-03-04 1987-11-17 Raytheon Company Adder/substractor for variable length numbers

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3290494A (en) * 1963-02-13 1966-12-06 Bunker Ramo Binary addition apparatus
US3320410A (en) * 1964-06-09 1967-05-16 Sperry Rand Corp Register including inter-stage multivibrator temporary storage
US3417236A (en) * 1964-12-23 1968-12-17 Ibm Parallel binary adder utilizing cyclic control signals
US3375358A (en) * 1965-08-30 1968-03-26 Fabri Tek Inc Binary arithmetic network
US3488481A (en) * 1966-04-20 1970-01-06 Fabri Tek Inc Parallel binary adder-subtractor without carry storage

Also Published As

Publication number Publication date
NL6908710A (fr) 1970-12-09
GB1313169A (en) 1973-04-11
US3676657A (en) 1972-07-11
DE2025079A1 (de) 1970-12-10

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Legal Events

Date Code Title Description
ST Notification of lapse