FR2020602A1 - - Google Patents

Info

Publication number
FR2020602A1
FR2020602A1 FR6930684A FR6930684A FR2020602A1 FR 2020602 A1 FR2020602 A1 FR 2020602A1 FR 6930684 A FR6930684 A FR 6930684A FR 6930684 A FR6930684 A FR 6930684A FR 2020602 A1 FR2020602 A1 FR 2020602A1
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR6930684A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2020602A1 publication Critical patent/FR2020602A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/02—Comparing digital values
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Mathematical Analysis (AREA)
  • Computing Systems (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Logic Circuits (AREA)
FR6930684A 1968-10-14 1969-09-02 Withdrawn FR2020602A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US76723668A 1968-10-14 1968-10-14

Publications (1)

Publication Number Publication Date
FR2020602A1 true FR2020602A1 (fr) 1970-07-17

Family

ID=25078894

Family Applications (1)

Application Number Title Priority Date Filing Date
FR6930684A Withdrawn FR2020602A1 (fr) 1968-10-14 1969-09-02

Country Status (5)

Country Link
US (1) US3584205A (fr)
CA (1) CA932465A (fr)
DE (1) DE1948387A1 (fr)
FR (1) FR2020602A1 (fr)
GB (1) GB1238273A (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1957302A1 (de) * 1969-11-14 1971-05-19 Telefunken Patent Volladdierer
AU466192B2 (en) * 1971-07-22 1975-10-23 Tokyo Shibaura Electric Co. Suz Sequence controller
US3787673A (en) * 1972-04-28 1974-01-22 Texas Instruments Inc Pipelined high speed arithmetic unit
US3818202A (en) * 1973-02-20 1974-06-18 Sperry Rand Corp Binary bypassable arithmetic linear module
US3849638A (en) * 1973-07-18 1974-11-19 Gen Electric Segmented associative logic circuits
US4160290A (en) * 1978-04-10 1979-07-03 Ncr Corporation One-bit multifunction arithmetic and logic circuit
JP2737173B2 (ja) * 1988-10-25 1998-04-08 日本電気株式会社 記号列照合装置とその制御方法
RU2762547C1 (ru) * 2021-04-02 2021-12-21 федеральное государственное бюджетное образовательное учреждение высшего образования "Ульяновский государственный технический университет" Пороговый модуль

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3261000A (en) * 1961-12-22 1966-07-12 Ibm Associative memory logical connectives
US3371320A (en) * 1965-03-12 1968-02-27 Sperry Rand Corp Multipurpose matrix
US3454310A (en) * 1966-05-23 1969-07-08 Electronic Associates Boolian connective system

Also Published As

Publication number Publication date
GB1238273A (fr) 1971-07-07
DE1948387A1 (de) 1970-07-02
CA932465A (en) 1973-08-21
US3584205A (en) 1971-06-08

Similar Documents

Publication Publication Date Title
AU1946070A (fr)
AU428130B2 (fr)
AU5184069A (fr)
AU6168869A (fr)
FR2020602A1 (fr)
AU416157B2 (fr)
AU429879B2 (fr)
AU4811568A (fr)
AU421558B1 (fr)
AU3789668A (fr)
AU4744468A (fr)
AU3224368A (fr)
AU4558658A (fr)
BE709496A (fr)
BE726406A (fr)
AU479393A (fr)
BE725708A (fr)
BE721390A (fr)
BE719099A (fr)
BE715282A (fr)
BE726715A (fr)
AU463027A (fr)
BE581157A (fr)
AU4503667A (fr)
AU4464266A (fr)

Legal Events

Date Code Title Description
ST Notification of lapse