FR2014870A7 - - Google Patents
Info
- Publication number
- FR2014870A7 FR2014870A7 FR6926280A FR6926280A FR2014870A7 FR 2014870 A7 FR2014870 A7 FR 2014870A7 FR 6926280 A FR6926280 A FR 6926280A FR 6926280 A FR6926280 A FR 6926280A FR 2014870 A7 FR2014870 A7 FR 2014870A7
- Authority
- FR
- France
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D10/00—Bipolar junction transistors [BJT]
- H10D10/01—Manufacture or treatment
- H10D10/051—Manufacture or treatment of vertical BJTs
- H10D10/056—Manufacture or treatment of vertical BJTs of vertical BJTs having the main current going through the whole substrate, e.g. power BJTs
- H10D10/058—Manufacture or treatment of vertical BJTs of vertical BJTs having the main current going through the whole substrate, e.g. power BJTs having multi-emitter structures, e.g. interdigitated, multi-cellular or distributed emitters
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/482—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes for individual devices provided for in groups H10D8/00 - H10D48/00, e.g. for power transistors
- H10W20/484—Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19681764766 DE1764766C3 (de) | 1968-08-01 | Verfahren zum Herstellen eines Transistors |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| FR2014870A7 true FR2014870A7 (cg-RX-API-DMAC10.html) | 1970-04-24 |
Family
ID=5698122
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR6926280A Expired FR2014870A7 (cg-RX-API-DMAC10.html) | 1968-08-01 | 1969-07-31 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US3673012A (cg-RX-API-DMAC10.html) |
| FR (1) | FR2014870A7 (cg-RX-API-DMAC10.html) |
| GB (1) | GB1228700A (cg-RX-API-DMAC10.html) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3895977A (en) * | 1973-12-20 | 1975-07-22 | Harris Corp | Method of fabricating a bipolar transistor |
-
1969
- 1969-07-17 GB GB1228700D patent/GB1228700A/en not_active Expired
- 1969-07-29 US US845773A patent/US3673012A/en not_active Expired - Lifetime
- 1969-07-31 FR FR6926280A patent/FR2014870A7/fr not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| GB1228700A (cg-RX-API-DMAC10.html) | 1971-04-15 |
| DE1764766A1 (de) | 1971-11-11 |
| DE1764766B2 (de) | 1976-01-08 |
| US3673012A (en) | 1972-06-27 |