FR2006005A1 - - Google Patents
Info
- Publication number
- FR2006005A1 FR2006005A1 FR6911099A FR6911099A FR2006005A1 FR 2006005 A1 FR2006005 A1 FR 2006005A1 FR 6911099 A FR6911099 A FR 6911099A FR 6911099 A FR6911099 A FR 6911099A FR 2006005 A1 FR2006005 A1 FR 2006005A1
- Authority
- FR
- France
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
- H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
- H03K19/212—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using bipolar transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/007—Fail-safe circuits
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19681763149 DE1763149A1 (de) | 1968-04-10 | 1968-04-10 | Gatterschaltung einer gegen innere Fehler geschuetzten digital-binaeren Steuerung |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| FR2006005A1 true FR2006005A1 (de) | 1969-12-19 |
Family
ID=5697388
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR6911099A Withdrawn FR2006005A1 (de) | 1968-04-10 | 1969-04-10 |
Country Status (3)
| Country | Link |
|---|---|
| DE (1) | DE1763149A1 (de) |
| FR (1) | FR2006005A1 (de) |
| NL (1) | NL6905486A (de) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2554291A1 (fr) * | 1983-10-26 | 1985-05-03 | Jeumont Schneider | Circuit logique " et " a securite intrinseque |
-
1968
- 1968-04-10 DE DE19681763149 patent/DE1763149A1/de active Pending
-
1969
- 1969-04-09 NL NL6905486A patent/NL6905486A/xx unknown
- 1969-04-10 FR FR6911099A patent/FR2006005A1/fr not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2554291A1 (fr) * | 1983-10-26 | 1985-05-03 | Jeumont Schneider | Circuit logique " et " a securite intrinseque |
| EP0141716A1 (de) * | 1983-10-26 | 1985-05-15 | JEUMONT-SCHNEIDER Société anonyme dite: | Fehlersichere logische UND-Schaltung |
Also Published As
| Publication number | Publication date |
|---|---|
| DE1763149A1 (de) | 1971-09-16 |
| NL6905486A (de) | 1969-10-14 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| ST | Notification of lapse |