FR1590660A - - Google Patents
Info
- Publication number
- FR1590660A FR1590660A FR161600A FR1590660DA FR1590660A FR 1590660 A FR1590660 A FR 1590660A FR 161600 A FR161600 A FR 161600A FR 1590660D A FR1590660D A FR 1590660DA FR 1590660 A FR1590660 A FR 1590660A
- Authority
- FR
- France
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30018—Bit or string instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
- G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
- H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
- H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
- H04Q3/54508—Configuration, initialisation
- H04Q3/54533—Configuration data, translation, passwords, databases
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Databases & Information Systems (AREA)
- Computer Networks & Wireless Communication (AREA)
- Executing Machine-Instructions (AREA)
- Controls And Circuits For Display Device (AREA)
- Image Generation (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR161600 | 1968-08-02 |
Publications (1)
Publication Number | Publication Date |
---|---|
FR1590660A true FR1590660A (en) | 1970-04-20 |
Family
ID=8653350
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR161600A Expired FR1590660A (en) | 1968-08-02 | 1968-08-02 |
Country Status (5)
Country | Link |
---|---|
US (1) | US3602898A (en) |
JP (1) | JPS4842008B1 (en) |
BE (1) | BE736923A (en) |
CH (1) | CH505370A (en) |
FR (1) | FR1590660A (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2062912B (en) * | 1979-09-29 | 1983-09-14 | Plessey Co Ltd | Data processing system including internal register addressing arrangements |
ATE67326T1 (en) * | 1986-07-02 | 1991-09-15 | Unisys Corp | PROGRAM CONTROLLED PARTIALLY DISTRIBUTED MASK DEVICE IN A PROGRAMMABLE UNIT WITH VARIABLE DATA PATH WIDTHS. |
US6268228B1 (en) * | 1999-01-27 | 2001-07-31 | International Business Machines Corporation | Electrical mask identification of memory modules |
US9003170B2 (en) | 2009-12-22 | 2015-04-07 | Intel Corporation | Bit range isolation instructions, methods, and apparatus |
-
1968
- 1968-08-02 FR FR161600A patent/FR1590660A/fr not_active Expired
-
1969
- 1969-07-15 US US841763A patent/US3602898A/en not_active Expired - Lifetime
- 1969-07-30 CH CH1157469A patent/CH505370A/en not_active IP Right Cessation
- 1969-08-01 BE BE736923D patent/BE736923A/xx unknown
- 1969-08-01 JP JP44060431A patent/JPS4842008B1/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
DE1938346A1 (en) | 1970-04-09 |
US3602898A (en) | 1971-08-31 |
CH505370A (en) | 1971-03-31 |
JPS4842008B1 (en) | 1973-12-10 |
DE1938346B2 (en) | 1977-05-05 |
BE736923A (en) | 1970-02-02 |
Similar Documents
Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |