FR1475142A - High speed, multiple input adder - Google Patents
High speed, multiple input adderInfo
- Publication number
- FR1475142A FR1475142A FR56206A FR56206A FR1475142A FR 1475142 A FR1475142 A FR 1475142A FR 56206 A FR56206 A FR 56206A FR 56206 A FR56206 A FR 56206A FR 1475142 A FR1475142 A FR 1475142A
- Authority
- FR
- France
- Prior art keywords
- high speed
- multiple input
- input adder
- adder
- speed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
- G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
- G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- Quality & Reliability (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR56206A FR1475142A (en) | 1965-04-05 | 1966-04-04 | High speed, multiple input adder |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US44532065A | 1965-04-05 | 1965-04-05 | |
US44532165A | 1965-04-05 | 1965-04-05 | |
FR56206A FR1475142A (en) | 1965-04-05 | 1966-04-04 | High speed, multiple input adder |
Publications (1)
Publication Number | Publication Date |
---|---|
FR1475142A true FR1475142A (en) | 1967-03-31 |
Family
ID=27243072
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR56206A Expired FR1475142A (en) | 1965-04-05 | 1966-04-04 | High speed, multiple input adder |
Country Status (1)
Country | Link |
---|---|
FR (1) | FR1475142A (en) |
-
1966
- 1966-04-04 FR FR56206A patent/FR1475142A/en not_active Expired
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