FR1404247A - Increment adder - Google Patents

Increment adder

Info

Publication number
FR1404247A
FR1404247A FR985093A FR985093A FR1404247A FR 1404247 A FR1404247 A FR 1404247A FR 985093 A FR985093 A FR 985093A FR 985093 A FR985093 A FR 985093A FR 1404247 A FR1404247 A FR 1404247A
Authority
FR
France
Prior art keywords
increment adder
adder
increment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR985093A
Other languages
French (fr)
Inventor
Theo Stutz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rheinmetall Air Defence AG
Original Assignee
Oerlikon Contraves AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CH537062A external-priority patent/CH397773A/en
Priority claimed from CH1041763A external-priority patent/CH421185A/en
Application filed by Oerlikon Contraves AG filed Critical Oerlikon Contraves AG
Priority to FR985093A priority Critical patent/FR1404247A/en
Priority claimed from CH484965A external-priority patent/CH421186A/en
Application granted granted Critical
Publication of FR1404247A publication Critical patent/FR1404247A/en
Priority claimed from CH1255966A external-priority patent/CH441438A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/64—Digital differential analysers, i.e. computing devices for differentiation, integration or solving differential or integral equations, using pulses representing increments; Other incremental computing devices for solving difference equations
    • G06F7/66—Digital differential analysers, i.e. computing devices for differentiation, integration or solving differential or integral equations, using pulses representing increments; Other incremental computing devices for solving difference equations wherein pulses represent unitary increments only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/26—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being duration, interval, position, frequency, or sequence
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3832—Less usual number representations
    • G06F2207/3848—Unit distance code

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Optimization (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Nonlinear Science (AREA)
FR985093A 1962-05-04 1964-08-13 Increment adder Expired FR1404247A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR985093A FR1404247A (en) 1962-05-04 1964-08-13 Increment adder

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
CH537062A CH397773A (en) 1962-05-04 1962-05-04 Counter for certain signal characteristics and use thereof
CH1041763A CH421185A (en) 1963-08-23 1963-08-23 Logical network for processing two-phase incremental signal sequences
FR985093A FR1404247A (en) 1962-05-04 1964-08-13 Increment adder
CH484965A CH421186A (en) 1965-04-07 1965-04-07 Up / down counter for two-phase binary signal sequences
CH1255966A CH441438A (en) 1962-05-04 1966-08-30 Forward-backward counter

Publications (1)

Publication Number Publication Date
FR1404247A true FR1404247A (en) 1965-06-25

Family

ID=27509220

Family Applications (1)

Application Number Title Priority Date Filing Date
FR985093A Expired FR1404247A (en) 1962-05-04 1964-08-13 Increment adder

Country Status (1)

Country Link
FR (1) FR1404247A (en)

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