FR1380501A - Registre à décalage asynchrone autonome - Google Patents

Registre à décalage asynchrone autonome

Info

Publication number
FR1380501A
FR1380501A FR945526A FR945526A FR1380501A FR 1380501 A FR1380501 A FR 1380501A FR 945526 A FR945526 A FR 945526A FR 945526 A FR945526 A FR 945526A FR 1380501 A FR1380501 A FR 1380501A
Authority
FR
France
Prior art keywords
shift register
asynchronous shift
autonomous asynchronous
autonomous
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR945526A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sperry Corp
Original Assignee
Sperry Rand Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US221706A external-priority patent/US3166715A/en
Application filed by Sperry Rand Corp filed Critical Sperry Rand Corp
Priority to FR945526A priority Critical patent/FR1380501A/fr
Application granted granted Critical
Publication of FR1380501A publication Critical patent/FR1380501A/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
FR945526A 1962-09-06 1963-08-23 Registre à décalage asynchrone autonome Expired FR1380501A (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR945526A FR1380501A (fr) 1962-09-06 1963-08-23 Registre à décalage asynchrone autonome

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US221706A US3166715A (en) 1962-09-06 1962-09-06 Asynchronous self controlled shift register
FR945526A FR1380501A (fr) 1962-09-06 1963-08-23 Registre à décalage asynchrone autonome

Publications (1)

Publication Number Publication Date
FR1380501A true FR1380501A (fr) 1964-12-04

Family

ID=26203017

Family Applications (1)

Application Number Title Priority Date Filing Date
FR945526A Expired FR1380501A (fr) 1962-09-06 1963-08-23 Registre à décalage asynchrone autonome

Country Status (1)

Country Link
FR (1) FR1380501A (fr)

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