FR1368171A - Appareil de synchronisation - Google Patents

Appareil de synchronisation

Info

Publication number
FR1368171A
FR1368171A FR936679A FR936679A FR1368171A FR 1368171 A FR1368171 A FR 1368171A FR 936679 A FR936679 A FR 936679A FR 936679 A FR936679 A FR 936679A FR 1368171 A FR1368171 A FR 1368171A
Authority
FR
France
Prior art keywords
synchronization device
synchronization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR936679A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US198841A external-priority patent/US3266024A/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to FR936679A priority Critical patent/FR1368171A/fr
Application granted granted Critical
Publication of FR1368171A publication Critical patent/FR1368171A/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/22—Handling requests for interconnection or transfer for access to input/output bus using successive scanning, e.g. polling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/22—Arrangements affording multiple use of the transmission path using time-division multiplexing
    • H04L5/225—Arrangements affording multiple use of the transmission path using time-division multiplexing combined with the use of transition coding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
FR936679A 1962-05-31 1963-05-31 Appareil de synchronisation Expired FR1368171A (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR936679A FR1368171A (fr) 1962-05-31 1963-05-31 Appareil de synchronisation

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US198841A US3266024A (en) 1962-05-31 1962-05-31 Synchronizing apparatus
FR936679A FR1368171A (fr) 1962-05-31 1963-05-31 Appareil de synchronisation

Publications (1)

Publication Number Publication Date
FR1368171A true FR1368171A (fr) 1964-07-31

Family

ID=26201619

Family Applications (1)

Application Number Title Priority Date Filing Date
FR936679A Expired FR1368171A (fr) 1962-05-31 1963-05-31 Appareil de synchronisation

Country Status (1)

Country Link
FR (1) FR1368171A (fr)

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