FR1259397A - Logical binary flip-flop - Google Patents

Logical binary flip-flop

Info

Publication number
FR1259397A
FR1259397A FR2216A FR2216A FR1259397A FR 1259397 A FR1259397 A FR 1259397A FR 2216 A FR2216 A FR 2216A FR 2216 A FR2216 A FR 2216A FR 1259397 A FR1259397 A FR 1259397A
Authority
FR
France
Prior art keywords
flop
logical binary
binary flip
flip
logical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR2216A
Other languages
French (fr)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cegelec SA
Original Assignee
Cegelec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cegelec SA filed Critical Cegelec SA
Priority to FR2216A priority Critical patent/FR1259397A/en
Priority to BE599894A priority patent/BE599894A/en
Application granted granted Critical
Publication of FR1259397A publication Critical patent/FR1259397A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
FR2216A 1960-02-19 1960-02-19 Logical binary flip-flop Expired FR1259397A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR2216A FR1259397A (en) 1960-02-19 1960-02-19 Logical binary flip-flop
BE599894A BE599894A (en) 1960-02-19 1961-02-06 Logical binary flip-flop.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR2216A FR1259397A (en) 1960-02-19 1960-02-19 Logical binary flip-flop

Publications (1)

Publication Number Publication Date
FR1259397A true FR1259397A (en) 1961-04-28

Family

ID=8568437

Family Applications (1)

Application Number Title Priority Date Filing Date
FR2216A Expired FR1259397A (en) 1960-02-19 1960-02-19 Logical binary flip-flop

Country Status (2)

Country Link
BE (1) BE599894A (en)
FR (1) FR1259397A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2470496A1 (en) * 1979-11-19 1981-05-29 Control Data Corp REGISTER

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2470496A1 (en) * 1979-11-19 1981-05-29 Control Data Corp REGISTER

Also Published As

Publication number Publication date
BE599894A (en) 1961-05-29

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