FR1249616A - Additionneur parallèle - Google Patents
Additionneur parallèleInfo
- Publication number
- FR1249616A FR1249616A FR819645A FR819645A FR1249616A FR 1249616 A FR1249616 A FR 1249616A FR 819645 A FR819645 A FR 819645A FR 819645 A FR819645 A FR 819645A FR 1249616 A FR1249616 A FR 1249616A
- Authority
- FR
- France
- Prior art keywords
- parallel adder
- adder
- parallel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- General Engineering & Computer Science (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR819645A FR1249616A (fr) | 1959-02-26 | 1960-02-25 | Additionneur parallèle |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US79581659A | 1959-02-26 | 1959-02-26 | |
FR819645A FR1249616A (fr) | 1959-02-26 | 1960-02-25 | Additionneur parallèle |
Publications (1)
Publication Number | Publication Date |
---|---|
FR1249616A true FR1249616A (fr) | 1960-12-30 |
Family
ID=26185096
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR819645A Expired FR1249616A (fr) | 1959-02-26 | 1960-02-25 | Additionneur parallèle |
Country Status (1)
Country | Link |
---|---|
FR (1) | FR1249616A (fr) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3198939A (en) * | 1961-10-17 | 1965-08-03 | Rca Corp | High speed binary adder-subtractor with carry ripple |
-
1960
- 1960-02-25 FR FR819645A patent/FR1249616A/fr not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3198939A (en) * | 1961-10-17 | 1965-08-03 | Rca Corp | High speed binary adder-subtractor with carry ripple |
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