FR1248465A - Method and device for binary addition and subtraction - Google Patents

Method and device for binary addition and subtraction

Info

Publication number
FR1248465A
FR1248465A FR809065A FR809065A FR1248465A FR 1248465 A FR1248465 A FR 1248465A FR 809065 A FR809065 A FR 809065A FR 809065 A FR809065 A FR 809065A FR 1248465 A FR1248465 A FR 1248465A
Authority
FR
France
Prior art keywords
subtraction
binary addition
binary
addition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR809065A
Other languages
French (fr)
Inventor
J Jeanniot
M Agon
Y Poupon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Compagnie IBM France SAS
Original Assignee
Compagnie IBM France SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Compagnie IBM France SAS filed Critical Compagnie IBM France SAS
Priority to FR809065A priority Critical patent/FR1248465A/en
Application granted granted Critical
Publication of FR1248465A publication Critical patent/FR1248465A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/504—Adding; Subtracting in bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
FR809065A 1959-11-02 1959-11-02 Method and device for binary addition and subtraction Expired FR1248465A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR809065A FR1248465A (en) 1959-11-02 1959-11-02 Method and device for binary addition and subtraction

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR809065A FR1248465A (en) 1959-11-02 1959-11-02 Method and device for binary addition and subtraction

Publications (1)

Publication Number Publication Date
FR1248465A true FR1248465A (en) 1960-12-16

Family

ID=8720791

Family Applications (1)

Application Number Title Priority Date Filing Date
FR809065A Expired FR1248465A (en) 1959-11-02 1959-11-02 Method and device for binary addition and subtraction

Country Status (1)

Country Link
FR (1) FR1248465A (en)

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