FR1134749A - Addition circuit - Google Patents

Addition circuit

Info

Publication number
FR1134749A
FR1134749A FR1134749DA FR1134749A FR 1134749 A FR1134749 A FR 1134749A FR 1134749D A FR1134749D A FR 1134749DA FR 1134749 A FR1134749 A FR 1134749A
Authority
FR
France
Prior art keywords
addition circuit
circuit
addition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
Other languages
French (fr)
Inventor
Pierre-Jean Foursin
Andre-Edouard-Joseph Chatelon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Laboratoire Central de Telecommunications SA
Original Assignee
Laboratoire Central de Telecommunications SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Laboratoire Central de Telecommunications SA filed Critical Laboratoire Central de Telecommunications SA
Application granted granted Critical
Publication of FR1134749A publication Critical patent/FR1134749A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
FR1134749D 1954-12-30 1954-12-30 Addition circuit Expired FR1134749A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1134749T 1954-12-30

Publications (1)

Publication Number Publication Date
FR1134749A true FR1134749A (en) 1957-04-17

Family

ID=9639472

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1134749D Expired FR1134749A (en) 1954-12-30 1954-12-30 Addition circuit

Country Status (1)

Country Link
FR (1) FR1134749A (en)

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