FR1124987A - Improvements to parallel adders for calculating machines - Google Patents

Improvements to parallel adders for calculating machines

Info

Publication number
FR1124987A
FR1124987A FR1124987DA FR1124987A FR 1124987 A FR1124987 A FR 1124987A FR 1124987D A FR1124987D A FR 1124987DA FR 1124987 A FR1124987 A FR 1124987A
Authority
FR
France
Prior art keywords
calculating machines
parallel adders
adders
parallel
machines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
Other languages
French (fr)
Inventor
Roland Dufour
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SOC NOUVELLE OUTIL RBV RADIO
Original Assignee
SOC NOUVELLE OUTIL RBV RADIO
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SOC NOUVELLE OUTIL RBV RADIO filed Critical SOC NOUVELLE OUTIL RBV RADIO
Application granted granted Critical
Publication of FR1124987A publication Critical patent/FR1124987A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
FR1124987D 1955-03-15 1955-03-15 Improvements to parallel adders for calculating machines Expired FR1124987A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1124987T 1955-03-15

Publications (1)

Publication Number Publication Date
FR1124987A true FR1124987A (en) 1956-10-22

Family

ID=9634213

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1124987D Expired FR1124987A (en) 1955-03-15 1955-03-15 Improvements to parallel adders for calculating machines

Country Status (1)

Country Link
FR (1) FR1124987A (en)

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