FI92533C - Sigma-delta modulator - Google Patents

Description

1 92533

Sigma-delta modulator

The invention relates to a sigma-delta modulator system having a first sigma-delta modulator which uses at least two stages of integration and a quantization means for quantizing the main signal; means for generating an error signal representing a quantization error of the first modulator or an error of the integrated signal estimate; a second sigma-delta modulator step 10, which provides at least two stages of integration and a quantization means, for quantizing said error signal; a derivation means having a transfer function substantially the same as the cover function of the common transfer function of the integration stages of the first modulator step for deriving the output signal of the second modulator step; means for delaying the quantized main signal by a delay of the second modulator wave; and means for subtracting the deviated error signal from the delayed quantized pass signal.

In Sigma-delta modulators (known as myds delta-sigma modulators), the signal is quantized using only a small number of quantization levels (2-256, corresponding to a 1-8 bit A / D converter) at a high rate that is generally 32-512 times higher signal frequency-25 I do. The ratio of the Nyquist frequency sampling of the signal band (2 times the hydrogen signal band) to the high sampling frequency used is called the mytis oversampling ratio (M). A quantizer is a combination of an A / D and a D / A converter in which an analog signal is converted to a discrete-valued digital number by a 30 A / D converter, and

immediately after tSm3 is converted back to the analog jfln volume (value) by a D / A converter. Quantization error (eq) means the difference voltage (value) between the analog input voltage and the analog output voltage, quantum-35 operating noise means the spectrum of the quantization error.

2 92533 (Qe), which in the case of a sigma-delta modulator can be considered as white noise with an rms value (E) of 1-bit celite (q / 2) 2, where q is the vSli of the quantization levels. The structure of the Sig-ma-delta modulator is intended to be such that a different transfer function (NTF) at the output of the modulator is obtained for the error generated in the quantizer than for the signal from input to output (STF). The purpose is to provide for the quantization error a transfer function NTF with the highest possible attenuation 10 in the desired fast band, and at the same time the signal transfer function STF is possible from the fast fast band. STF and NTF depend on each other according to the structure used. The degree of the modulator means the degree of the NTF function, or the number of integrators in the modulator. By increasing the number of degrees in the modulator, the amount of quantization noise can be reduced from the fast band. Another way to reduce the quantization noise from the fast band is to increase the oversampling ratio, however, increasing the oversampling ratio increases the sampling frequency, which is limited by the components used in the implementation. Therefore, the only way to improve the ratio of signal (S) to quantization noise (Nq) in the fasting band (S / Nq) is to increase the degree of the modulator or to try to improve the NTF function by achieving a higher attenuation in the fasting band with the same degree and oversampling ratio.

However, in a conventional manner, a sigma-delta modulator formed by directly connected integrators is difficult to implement in use due to the variation caused by the feedback loop. Therefore, higher order sigma-delta modulators are formed in a cascade of two or more stable lower order sigma-delta modulators. In the cascade, the quantization error of the first modulator is passed to the second modulator, and the outputs of the blocks are combined to reduce the amount of quantization noise in the signal band. In "A 16-bit Oversampling A-to-D Conversion Using Triple-Integration Noise Shaping," IEEE Journal of Solid State Cir-5 cuits, Vol. SC-22, no. 6, December 1987, pp. 921-929, describes the cascade coupling of first order sigma-delta modulators by the so-called MASH technique. FI patent 80548 describes cascade couplings of higher order sigma-delta modulators.

It is an object of the invention to cascade two sigma-delta modulator blocks in such a way that a better S / N2 is achieved than was previously possible with modulator systems of the same degree with the same oversampling ratios.

This is achieved by a sigma-delta modulator system of the type described in the preamble, which according to the invention is characterized in that the second modulator has a negative feedback from the output of at least one integration stage to the input of the preceding integration stage 20, and that it is input.

According to the invention, two n-degree 1-bit sigma-delta modulator blocks implemented with a quantizer are cascaded so that the last modulator-25 block quantizes the quantization error (value) of the modulation error generated in the first modulator block by the e-scale. the 1-bit data of the last block is filtered by a digital filter which is a cover function for the STF function of the first block and multiplied by a scaler C to reduce the 1-bit data of the first block delimited by the gate of the last modulator block. Thus, a reduced and quantized error of the first block quantized by the modulator-35 block is obtained from the output of the first block.

4 92533 The digital output thus obtained is the output of a 2 * n-degree sigma-del-ta modulator.

The modulator blocks used in the invention are of either the FF-tax MF type. According to the invention, the modu-5 generator block of each is of the same type. According to the invention, the zero pair of the NTF function can be shifted in the most recent block so that a smaller amount of quantization noise is achieved in the signal usage band than is possible with modulator systems of the same degree in the past 10 minutes. In all of the previously presented cascade circuits, all zeros of the NTF function that are numbered in degree numbers are at the 0 frequency. The basic idea of the invention is to use the new modulator structures to shift the noise modification function of the modulator system to higher frequencies so that the amount of quantization noise in the fasting band of the modulator system is reduced compared to conventional sigma-delta. With an excess feedback factor a in the error quantizing modulator block 20 connected from the output of the last integrator to the input of the previous integrator, the zero pair of the noise function is shifted from the 0 frequency to the complex conjugate frequency. and another in the direction of the positive frequency variable. The transmission zero pair of the noise function can be transferred as an addition to the last modulator in the cascade, feedback from the output of one integration stage to the input of the previous integration stage, whereby the value of the feedback field mddraa myOs transfer zero location. This feedback and noise function can only be implemented in the jaw modulator, so that after the yaw modulator, the digital function required in the cascade remains as a derivative to be realized in use.

I! 5,92533

For example, in a fourth-order modulator system according to the invention with two second-order modulators cascaded, an improvement in signal-to-signal quantization noise ratio (SNRQ) of about 10 dB can be achieved with transmission with a cascade structure in which all NTF function zeros are 0. juudella. This, in turn, means that it is possible to achieve an SNRQ of more than 20 bits with an oversampling ratio of 64 or a 16-bit SNRQ with an oversampling ratio of 32. An 8-stage 10 modulator system using a shift zero can achieve at least 20 bits of SNRQ with a sampling rate of 32. At the same modulus ku remains the same and the requirements of the digital filter required in the A / D converter structure remain the same compared to a modulator of 15 corresponding degrees, the zeros of the noise function of which are located at the O frequency. The reduction of the oversampling ratio for the same required performance and signal band facilitates the fabrication of faster A / D converters compared to previous solutions. When using Mytts kor-20 lower order (n> 2) modulator blocks, the accuracy requirements of the integrators and amplifiers required for implementation are relaxed.

The invention will now be described in more detail by means of exemplary embodiments with reference to the accompanying drawing, in which Figure 1 shows a block diagram of a 2 * n-degree sig-madelta modulator system according to the invention, Figures 2 and 3 show Multiple Feedback type and Feed-forward, respectively. Fig. 4 is a block diagram of a 2-stage modulator suitable for use as the modulator block SD1 of Fig. 1; Fig. 4 is a block diagram of a 2-stage modulator based on the quantization error coupling suitable for use as the modulator block SD2; illustrating the noise spectra of a 4-stage modulator system according to the invention 62525 and a known modulator system, Fig. 6 is a graph illustrating the noise spectra of the 4-stage, 6- and 8-stage modulator signaling systems of the invention according to the invention; A 2-stage modulator suitable for use Fig. 8 shows a block diagram of a 2-stage modulator suitable for use as the modulator block SD2 of Fig. 1. Fig. 9 is a graph illustrating the value of parameter a as a function of the zero function of the noise function. edge of the fast band) when the oversampling ratio is 32, and Fig. 10 is a graph illustrating the location of the transmission zero in the z-plane unit circles.

The present invention has a special field of application in oversampled A / D converters. Oversampling generally means that the sampling frequency Fs is substantially higher than the minimum sampling frequency determined by the Nyquist criterion, which is twice the maximum frequency of the signal. In general, the sampling frequency to be used in oversampling Kay-25 is an integer multiple of the Nyquist frequency, e.g., 32 or 64 (oversampling ratio).

However, the invention can be used in any application utilizing a higher order sigma-delta modulator.

Figure 1 shows a general level connection of two n-degrees SD1 and SD2 in a cascade according to the invention. The quantizable input signal Din is applied to the first modulator block SD1, which generates a quantized 1-bit output signal D ', which is delayed in the delay block 5 by a delay z'k to the 6th time of the k-clock period. The quantization error of the modulator block 1 or the error e of the integrated signal estimate scaled by a factor of 1 / C is applied to the other modulator block SD2 which generates the quantized error signal e '. The signal e' is derived by the digital -z_1) n, where n is the number of integrators in block SD1. from the quantized main signal D ", whereby the output signal of the system only D 'divides the modulator block SD2 by n-15 times the derived quantization noise, which is 2 * n degrees.

In use, it is preferred that the degree numbers of the modulator blocks SD1 and SD2 are the same and implemented with the same coefficient values. If the degree numbers of the modulator blocks SD1 and SD2 are different or the number of delays is different from each other, the digital filter block 3 becomes difficult to implement in use because the IIR part must be realized in addition to the FIR derivative. Therefore, the cascade coupling of modulator blocks SD1 and SD2 with different degrees of degree is of less interest for the implementation of the application. Thus, in preferred embodiments of the invention, the degree n of the derivative implemented by myOs block 3 is the same as the degree n of the modulator blocks SD1 and SD2 and eliminates the effect of the common transfer function of the integrators of the modulator block SD1 in the quantized error signal e '. The delay k to the water k of the delay block 30 must be the same as the delay of the modulator block SD2, i.e. the total delay of its integrators. In the practical solution, the delay k is the number of clock cycles of the degree number SD1 of the modulator block, i.e. n = k. The error signal is scaled by a factor of 1 / C before and by a factor of C to-35 the modulator block, scaling the signal level to 82553 to reduce the linear operating range of block SD2. The minimum value of the coefficient C is the ratio of the modulator coefficients bn / bi. However, the system operates with scaling factors C higher than this, although the SNRQ decreases by a factor of 5 to increase the factor.

The cascade coupling of the two sigma-delta modulators according to the invention does not in itself differ from the known cascade couplings in the block diagram level shown in Figure 1. However, according to the invention, the noise modification function of the entire modulator system can be improved by suitable structures for the modulator blocks SD1 and SD2, so that the quantization noise in the fasting band of the modulator is reduced. This is achieved according to the invention in that the new modulator structures shift the transmission zeros of the noise modification function of the system from zero frequency upside down, when in all known cascaded modulators the transmission zeros of the noise transmission function are located at zero. The graph of Fig. 5 shows the noise spectrum 52 of a known 4-stage cascade structure (FI patent publication 80548) and the noise spectrum 51 of a modulator system with a complex shift zero pair according to the invention, so that the x-axis value 1 corresponds to half the sampling frequency F the noise spectrum 51 has a zero point in the quantization noise at a frequency of 0.85 x Fs and thus the total amount of noise in the fasting band of the modulator system is smaller than in the conventional 4-stage modulator system (spectrum 52).

A pair of transfer zeroes at a frequency of 0.85 * Fs can be shifted from the 0 frequency by adding an additional negative feedback to the modulator block SD2 at the input of the at least one integration stage preceding the output stage. The shifting of the zeros of the noise function can be realized by such a feedback circuit 35 only in the last modulator block SD2, so that the digital function which the digital filter 3 tSyty implements is a realizable derivative. Therefore, in the system according to the invention, the modulators can be connected to the cascade only in pairs, as opposed to the known cascade structures, in which the number of cascade stages was limited only by the sense of the implementation of the connection.

The feedback according to the invention imposes some additional requirements on blocks SD1 and SD2. The integrators SD1 and SD2 of the modulator blocks 10 must be delayed (in the general case at least two clock cycles delay in the outermost quantized value feedback loop of the modulator including the integrator delays, and the delay of one or two clock cycles should be possible) transfer to the noise function. By delayed integrator is meant a block whose discrete-time transfer function is z ~ / (1-z-1), where the discrete-time frequency variable z corresponds to a delay of one clock cycle at time level 20, respectively. If there is one delay in the feedback loop box a (in Figures 3, 4, 7, 8 the powers of z d2 = 0), the transfer takes precisely the z-level unit dymphatic-25 and the treasure attenuation is obtained. point. If, on the other hand, there are two delays in the feedback loop a (in Figures 3, 4, 7, 8 the powers of z d2 = 1), the transfer is set to a line which is the tangent of the unit circle at the point (1.0), so that the exact transfer gives only 30. however, the zeros are located so high in the over-sampling ratios of the I-helia unit circle as 64 that there is no significant difference in the amount of quantization noise in the signal band compared to exactly zero. Figure 6 shows the simulated price spectra 61, 62 and 63, respectively, of the 4-, 6- and 8-stage modulator systems of the invention 35. The TS1 in blocks SD1 and SD2 are used from 2-, 3- and 4-stage sigma, respectively. modulators. MyOs spectra 61, 62 and 63 have a spectrum of zero at 0.85 x Fs / 2.

The following are exemplary embodiments of 2-stage modulator structures that can be used in the modulator system of the invention as blocks SD1 and SD2. Figure 2 shows a multi-feedback sigma-delta-modu-10 generator suitable for block SD1. In the following order, the modulator is connected in series to a mediator 20, an integration stage 21, a mediator 28, an integration stage 22 and a quantizer, i.e. a comparator 23, at the output of which a final quantized signal Dr. Quantizer 23 means a combination of 15 A / D and D / A converters. te D2 is converted by A / D converter 23A into a discrete digital number D 'which forms the output of the modulator and which is immediately converted back to that analog voltage Df (value) by D / A converter 23B to form a two-part negative feedback 23 quantizer 23 out of print. the voltage Df is connected by a scaling means 26 (feedback factor b2) to the second input of the mediator 20 to be subtracted from the input voltage and via a scaling means 27 to the second input of the mediator 28 25 to be subtracted from the output voltage D1 of the first hour integration stage 21. The signal proportional to the quantization error of the modulator is formed by applying the input voltage D2 of the quantizer 23 and the voltage Df converted from the output signal D 'to the reducers 30 29, which subtract them from each other to form a quantization error voltage e. (at least b2 / b1), lowering its level to suit the next modulator block SD2.

Figure 3 shows a corresponding Feed-forward type for 11,92533 sigma-delta modulator blocks SD1. When connected in series, the modulator handles the mediator 36, the integration stage 31 and the integration stage 32. The output voltage D3 of the integration stage 31 is connected to the adder 35 via a scaler 33 (switch-5 field coefficient bx). 35. The sum-main 35 generates a sum voltage that is applied to the quantum soy 37 and the second input of the mediator 38. The Kvan-10 converter 37 again consists of A / D and D / A converters 37A and 37B. The output signal D 'of the quantizer 37 is fed back (via the converter 37B) to the intermediaries 36 to be reduced to the input stage Din input to the integration stage 31. The quantized output D 'is connected (via a converter 15 37B) to the mediators 38 to be subtracted from the quantum soy input voltage D5 so as to form a quantization error voltage e, which is scaled by the scaling step 39 to fit the modulator block SD2.

Figure 4 shows an eras Multiple Feedback sig-20 ma-delta modulator suitable for use with block SD1 implemented with the modulators of Figures 2 or 3. In the following order, the modulator of Fig. 4 uses a scaling means 46 (scaling factor 1 + a) connected in series, which may be included in the scaling gap 25 of Fig. 2, a mediator 47, an integration stage 41, a mediator 48, an integration stage 42, a delay block 44 and a quantizer 43. A / D and D / A converters 43A and 43B. The output signal e 'of the quantizer is (via converter 43B) feedback via scaler 45B (feedback factor b2) to the second input of mediator 47 to be subtracted from the error voltage e to be input to before it 35 is fed to the integration stage 42. The output signal of the quantizer 43, i.e. the quantization error signal e ', is applied to the derivative 3 of Fig. 1. The delay of the delay block 44 depends on the delay d2 of the second integration stage 42, d2 = 0, z' ° when d2 = 1 . In order for the transfer to be realized, there must be a delay of two clock cycles in the outer feedback loop. The combined delay of the delay block 44 and the integrator 42 is thus z "1 (one clock cycle).

In order to provide the transmission zeros according to the invention, the output voltage e2 10 of the integration stage 42 is feedback via a scaling motor 49 having a feedback factor a, the integration stage 42 and 41 are decremented from the output stage to the third input of the reducer 47 to be reduced to the third input stage. The graph of Fig. 9 illustrates the dependence of the position of the transfer zero on the coefficient of the circuit of Fig. 4 when the value of the coefficient a is between 0 and 0.02 and the value of the X-axis corresponds to half the sampling frequency when the oversampling ratio is 32.

Sigma delta modulators can be connected to a cascade of myGs coupled to the modulator block SD1 integrated signal estimate error 3 for the next modulator block SD2 when the feed-forward modulator structure is used in both modulator blocks SD1 and SD2. In error, it is possible to achieve a better signal-to-noise ratio (S / (N + Nq)) because the required Jannite scaling at the input of the first modulator block is smaller than in the previously presented cascade structures. The sensitivity of the modulator magnifier to the noise (N) of the circuit elements is at the input stage, and thus the performance of almost all modulators (more than 16 bits) is limited by the noise of the circuit elements of the first integrator. Smaller With Janni scaling, the physical noise (N) of the circuit elements divides 35 relatively smaller.

li 13 92533

Figure 7 shows a modulator structure suitable for use as a modulator block SD1 in a different modulator system. In the following order, the feed-forward modulator of Fig. 7 uses the serial switch-5, the integration stage 71 and the integration stage 72 as a series switch. The output voltage D6 of the integration stage 71 is connected b2) through an adder 75, the output voltage D8 generated by its output-10 is input to the quantizer 73. The quantizer 73 is again formed by the A / D and D / A converters 73A and 73B. The quantized output signal D 'of the quantizer 73 is input to the second input of the mediator 76 to be subtracted from the input input voltage Din of the input 15 to the integration stage 71. The output signal D 'of the quantizer 73 is connected (via the converter 73B) to the input of the myds mediator 77 to be subtracted from the output voltage D7 of the integration stage 72, i.e. the integrated signal estimate error, so as to generate which is scaled in the scaling medium 78 by a factor of 1 / C and fed to the modulator block SD2. Alternatively, the output voltage D7 of the integration stage 72 may directly form the error bands-'25 tea e, with blocks 77 and 79 splitting.

Figure 8 shows a feed-forward type sigma-delta modulator structure suitable for use as a modulator block SD2 when block SD1 is implemented with the modulator of Figure 2, 3 or 7. In Fig. 8, in the following order, the modulator 30 connects the mediator 86, the integration stage 81 and the integration stage 82 in series. The output voltage e5 of the integration stage 81 is connected via to adder 85. The output voltage e8 of adder 85 is applied to quantizers 83. Quantizer 83 again consists of A / D and D / A converters 83A and 83B. The output of the quantizer generates a quantized error signal e 'which is input to the derivative block 3 of Fig. 1 and (via converter 83B) to the second input of the mediator 86 to be subtracted from the error stage e to is a feedback factor a, feedback to one input of the mediator 86 at the input of the previous integration stage 81 to be subtracted from the error voltage e.

In the figures shown, all blocks, i.e., integrator-15s, are normalized and unscaled, however, integrators are voltage-scaled in applications. For clarity, voltage scales have been omitted for integrators.

The figures and the related description are intended only to illustrate the present invention. The details of the modulator system according to the invention may vary according to the appended claims.

II

Claims (10)

15 92533 A sigma-delta modulator system comprising a first sigma-delta modulator (SD1, SD2) 5 comprising at least two stages of integration (21.22, 31,32,71,72) and a quantization means (23,37,73) to quantize the main signal, means (29,38,77) for generating an error signal (e) representing the quantization error of the first modulator (SD1) or the error of the integrated signal estimate 10, the second sigma-delta modulator means (SD2) comprising two , 81,82) and a quantization means (43,83) for quantizing said error signal, a derivation means (3) having a transfer function substantially the same as the inverse function of the common transfer function of the first modulator integration stages, the output 20 of the second modulator means, the output of the second modulator means to delay the quantized main signal by a delay of the second modulator means, and means (6) for delaying the derived error signal. hentåmiseksi viivåstetystå quantized pååsignaalista, η t u n e t. characterized in that the second modulator (SD2) has at least 25 outputs of one integration stage (42.82) with a non-quantized negative feedback to the input of the preceding integration stage (41.81), and that there is at least one delay in the feedback loop. A system according to claim 1, characterized in that the value of the feedback coefficient of said negative feedback determines the position of the transmission zero in the noise spectrum of the modulator and is preferably between 0 and 0.02. System according to Claim 1 or 2, characterized in that the negative feedback loop in the output of the quantized value 16 92533 has at least two delays and the feedback loop in the transfer zero has a delay of one or two clock cycles. System according to Claim 1 or 2, characterized in that both the feedback degree of integration and the preceding degree of integration are delayed. A jar-10 system according to any one of claims 1 to 4, characterized in that said means for generating an error signal is used to reduce the input and output signals of the quantizer (23,37) of the first modulator (SD1) by the mediator (29,38). to produce a representative error signal 15. System according to one of Claims 1 to 4, characterized in that the first modulator means (SD1) is a modulator of the feed-forward type, and in that said error signal is the output signal of the last stage of integration of the first modulator (SD1). arctic fox. A system according to claim 6, characterized in that the first modulator line (SD1) is a Feedforward type modulator, and in that said error signal generating means matches the first modulator line to its output signal and quantizes the output signal and quantizer of the second integrator signal. an integrated signal estimate for producing an error signal representative of the error, and a quantizer of the first scaler (79) for scaling the output signal by a scaling factor x before input to the mediator, where 0 <x <4 * bl / b2. A system according to any one of the preceding claims, characterized in that it scales the second (I) 92533 to scale the error signal of its scaling means (25,39,78) by a scaling factor before the second modulator step and the third scaling means (4). to scale to a second scaling factor substantially equal to the cover number of the first factor before subtracting from the quantized pass signal. System according to one of the preceding claims, characterized in that the degree values of the first and second modulator steps are the same. A system according to claim 9, characterized in that the first and second modulator means are second order modulators. 18 92533