FI89222B - FOERFARANDE OCH KOPPLINGSANORDNING FOER INSAMLING AV SJAELVOEVERVAKNINGSINFORMATION I INFORMATIONSOEVERFOERINGSANORDNINGAR - Google Patents

Abstract

Method and circuit arrangement for collecting self-monitoring information in information transmission systems containing plug-in components. To enable identification data of the individual components to be updated in simple fashion and to be polled by a signal collector, the identification data is read into EEPROMs by means of a setup computer and polled by means of the signal collector using address selection and clock control. The method can be employed to particularly advantageous effect in conjunction with devices for recording error messages in information transmission systems. <IMAGE>

Description

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Method and switching arrangement for collecting self-monitoring information in communication devices

The invention relates to a method according to the preamble of claim 1 for collecting germ control information in electronic data transmission technology transmission devices and to a switching arrangement for implementing this method.

Such a method and such a coupling arrangement are previously known from DE-A-35 06 945.

The known method makes it possible to collect self-monitoring information of several telecommunication devices or data transmission devices, to transmit them to the exchange by means of a signal collection device and to interpret them in a central interpretation device. Such self-monitoring information can be, for example, receiver alarms in analog or code error alarms in digital data transmission. In this case, the transmitted messages may also contain identification information and, in particular, device identifiers. If an error is detected, the data is read again.

DE-A-33 32 304 further discloses a switching arrangement with an EEPROM which is loaded by means of a programming computer. The function of this EEPROM is to store operating values such as the bit rate of the transmitter or receiver, the address of the remote control station or the like.

The object of the invention is to provide a method and a switching arrangement as described in the preamble of claim 1 for implementing this method, which enables the identification and retrieval of identification data of private units so that identification data can be easily updated with a small memory size and retrieved by a signal acquisition device.

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According to the invention, the set task is solved as described in the characterizing part of claim 1. BEPROM (Electrically Erasable Programmable Read Only Memory) is a read-only memory whose memory locations can be reset electronically and new information can be written to them again. The information is not lost when the voltage is lost. The query of the identification data is most preferably carried out continuously or in a cyclical order.

The identification information may be, in particular, the company reference number, the abbreviation or reference number of the device, the distribution quantities of the platforms, the manufacturer's identification number, the serial number and / or the catalog number.

At the same time, the signal collectors may belong to the signal collection device collecting the error messages or be part of their own device collecting the identification data.

These measures have the advantage that, in the case of communication devices with several push units, the identification data, which provide more detailed information on the identity of the monitored units, can be collected in a very economical way.

Furthermore, according to the invention, the identification data need to be completely transmitted from the signal collector to the central monitoring device only when the transmission device is put into operation. After this, only changes to the identification data are notified to the central monitoring device, so that the data to be transmitted is reduced.

Claim 2 discloses a preferred coupling arrangement for carrying out the method according to claim 1.

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In the switching arrangement according to the invention, the memory units may have their own input for incoming data and their own output for outgoing data or a common data input and output. In both cases, the connection arrangement is implemented with cheaper and less frequent bus wiring. In this case, only one central clock is required in an advantageous manner.

In the embodiment according to claim 3, the memory component preferably has addresses which can be set by means of a unit pointing device or which addresses come into place when the unit is placed on the memory component via a plug connector from a pointing device outside the unit, so that the address depends on the connector location.

In the embodiment of the device according to claim 4, each memory component has its own call line, so that regardless of the number of units interrogated by the signal collector, only one single plug contact is required in the unit for assignment. The development form according to claim 7 advantageously enables the transmission of identification data in connection with error messages of the same unit.

The measures according to claim 6 have the advantage that the monitored units do not in themselves need any equipment for decoding the parity bit or check fields or for error detection or correction.

The embodiments according to claims 7 and 8 allow units which as such do not require a power supply to be used in the development of identification data without having to be connected to a power supply for this purpose.

: · In the embodiment according to claim 9, the signal collector calls the units via the address bus, 4 ö 9 2 2 2 so that it is not necessary to transmit address information via the data lines.

The invention is explained in more detail by means of the embodiments shown in the figures.

Fig. 1 shows an apparatus for collecting monitoring information, Fig. 2 shows an insertable unit with plug-in units with memory components, Fig. 3 shows an apparatus for collecting identification data by address-directed call using serial address information, Fig. 4 shows a part of the apparatus of Fig. 3 with other details shows a pulse diagram for the device according to Fig. 4, Fig. 6 shows a part of the device for collecting identification data by paging, Fig. 7 shows a part of the device for collecting identification data and error messages together, Fig. 8 shows a timing diagram for the device according to Fig. 7 for reading error messages, Fig. 9 shows a timing diagram for reading error messages and identification information, Fig. 10 shows a memory component whose supply voltage is derived from clock pulses, and Fig. 11 shows a memory component, whose supply voltage input is connected to its paging conductor.

Figure 1 shows a signal receiving device with a tree-structured data network. Signal collectors are located at several levels of the network. A third network level signal collector 13 including a control device is connected to the data processing device 14. A second network level signal collector 12 comprising a 7R structured rack array is connected to the signal collector 13.

A plurality of rack signal collectors 11 are connected to the second network level signal collectors 12.

A plurality of signal collectors 10 are connected to each of the first network-level signal collectors 11 comprising a plurality of 7R-structured insertable units 2. The signal collectors 10 are each located in one of the plug-in units 3 and together with the other plug-in units 3 in a Bw7R-type plug-in unit.

By means of the signal collection device shown in Fig. 1, the identification data is made available to the data processing device 14 for further processing. By means of the service terminal 15 connected to one of the first network-level collectors 11, the identification data can be read at the beginning of the network.

All push-in units, i.e. the plug-in units 3 and the non-adjustable units 2 are provided with their own memory component. The memory component consists of the EEPROM and stores the identification information of that unit.

Figure 2 shows an insertable unit provided with memory components in this way. The insertable unit 2 comprises a plurality of memory components 30 provided by the data unit 3, which belong to different communication systems A and B, in their own plug-in unit. a signal collector 10 having a memory component 100 and a insertable unit 2 of the memory component 20 for itself.

As memory components 20, 100 or 30, EEPROMs with HCMOS technology in particular are used, which have a serial data input and a serial data output, so that a small space requirement, a small power dissipation, few connection cables and the possibility of reprogramming are obtained. For example, an EEPROMie is a 256-byte memory space housed in an 8-pin enclosure. The data input and output can be combined for two-wire operation.

Such a memory component is, for example, Motorola's EEPROM MCM 2814. The memory component has first and second inputs to enable the component, an operating mode input for setting 2-wire or 4-wire bus operation, ground connection, connection for supply voltage, connection for programmers , clock input and serial data input / -1out.

The memory components are provided with identification data at the manufacturing site, at the test facility or at the place of use by means of a programming device or a service terminal. The loading of EEPROMs by means of programming data tokens is known per se and will therefore not be explained in more detail.

The component storage inputs are preferably used to address the memory component. Both inputs for enabling the component are then set via the pull-up resistor to the supply voltage and, depending on the address, are either connected or not connected to ground. In this case, four addresses are obtained as combinations of earth-supply voltage. The individual memory components or pushbuttons are then called in such a way that their addresses are entered in the form of ears via data lines.

To set the address, the inputs for enabling the component are connected to the ground in a similar manner, most preferably at the rear of the unit in question. On the other hand, one component input input can be connected to ground and the other to a call wire, which is connected to ground when that component is called.

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Figure 3 shows a switching arrangement in which serial assignment of memory components via data lines 51 ... 5n is used. One of the four addresses can be set in each piezo unit 3. Thus, up to four memory components or pusher units can be assigned to each data line. All the plug-in units 3 are supplied with a clock signal collector signal 10 via a common clock conductor 6. The plug-in circuits 3 are further connected in groups via a data wire 51 ... 5n to a signal collector 10. The first group G1 of the plug-in units 3 is

In this way, the signal collector 10 can be queried n times for 4 push guns.

Figure 4 shows other details of the connection arrangement according to Figure 3. This switching arrangement is suitable for plug-in units with a maximum of 16 plug-in units 3. The clock is routed to all plug-in units via a common clock conductor 6. In each case, the four plug-in units 1 have in common one of the four data lines 51, 52, 53 or 54.

The selection of the desired memory component takes place in such a way that the signal collector 11 assigns the address of the memory component to be called to the data line 1 which leads to the group of memory components to which the memory component in question belongs.

The switching arrangement shown in Fig. 4 shows a signal from the plurality of insertable units connected to the ice 11 only the unit 2 and the plug-in units contained in this unit 2 in addition to the monitoring plug-in included in the signal collector 10 only one of the plug-in units 3. The signal collector 10 includes a microprocessor 100 via this, error messages from the plug-in unit 3 of the insertable unit 2. Each plug-in unit 3 contains a memory component 30.

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A predetermined own address is set in the memory component 30 by means of the device 4. This own address is determined by the address setting device 4 on the back wall of the plug, te. per plug-in unit or with the corresponding wiring of the insertable unit, ie per plug-in location. The device 4 is connected to the inputs AO and AI of the comparator 35. These connections. AO and AI are connected to the supply voltage via a pull-up resistor 41 or 42 and can optionally be connected to ground by means of a device 4.

The memory component 30 includes a comparator 35 which is controlled by the microprocessor 100 via a clock conductor 6 connected to the clock input 302 together with the start-stop logic 34 and the control logic 33. The comparator 35 compares the address received via the data line 54 with the address set in the device 4. If the two addresses match, the comparator 35 outputs a correspondence signal to the control logic 1le 33. The actual EEPROM 31 is provided with an X decoder 32 and a Y decoder 36. A control logic 33 is connected in front of the X decoder 32. A data register 37 is connected to the Y decoder 36. , which receives clock control from the control logic 33 via an internal clock conductor 6a and one input of which is connected to the data input and output 301 and the output of which is connected via the controller 38 to the data input and output 301.

The data cable 54, which is connected to the data input and output 301 of the plug-in circuit 3, is also routed to three other plug-in units not shown in the figure. The other data lines 51-53 lead to four other plug-in units, not shown in the figure, so that the insertable unit 2 can contain up to 16 other plug-in units with memory components in addition to the monitoring unit comprising the signal collector 10.

The reading of the identification information is provided by the signal collector 10, which for this purpose sends an inquiry message to the data line 54. The first data byte transmitted by the signal collector 10 contains both address bits. These bits are compared to the memory component 30 by an integrated comparator 35 to its own address. If the two addresses match, the memory component 30 of the called plug unit 3 sends an acknowledgment signal and then transmits all its identification data to the signal collector 10. The signal collector 10 acknowledges each received byte. If the signal collector 10 of the Joe signal collector is missing, the connection is disconnected.

After switching on the insertable unit 2 of the switching arrangement according to Figs. 3, 4 or 5, the signal collector 10 queries all the plug-in units 3 for their identification information and stores this information in its memory. The data is sorted by signal encoder 1 in member 10 and connected, if necessary, to the private systems of unit 2. In this form, the data processing system DVA can read the identification data via a signal collection system similar to the known device shown in Fig. 1, or they can be queried by means of a service terminal 15. The identification data of the plug-in gears 3 are queried or read cyclically by the so-called polling method. The DVA data processing system is only given new information in the event of a change, especially when replacing plug-in units.

Figure 5 shows a preferred response message for transmitting the identification data from the plug-in units 3 to the signal collector 10. The response message starts with a start signal ST1 associated with a part with a fixed bit string BF, address bits AO and A1 and a logic "1". The response message starts with a logical "0" by generating an acknowledgment signal 11a AS of the memory component.

This is followed by the characters Z1, Z2 ... Z (n-1), Zn, which contain identification information, a check field SF consisting of one or two bytes and a stop sign ST2. The acknowledgment signals AM given by the signal collector after each signal Z1 ... Z (n-1) have a logic level 0 in the case of correct reception. The acknowledgment signal AM associated with the check support field SF has a logic level 1.

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Fig. 6 shows a switching arrangement in which the plug-in units 3 contained in the insertable unit 2 are called by means of call leads 81 ... 8n. The signal collector 10 included in the monitoring plug-in unit activates the individual plug-in units via call leads 81 ... 8n. In this case, one of the call lines 81 ... 8n is set to a logical "zero" in each case. This paging line then releases the called EEPROM 30 in such a way that the identification data stored in it can be read. The reading of the identification data takes place in the same way as with the switching arrangement according to Fig. 4, te. by means of the pulse message according to Fig. 5.

In devices with more than one system or plug-in unit per plug-in unit, error messages and identification information are most preferably read together via the serial bus. A switching arrangement enabling such a common reading is shown in Figure 7.

Figure 7 shows a switching arrangement in which a number of plug-in units and a signal collector of an insertable unit are connected to each other via bus conductors. Of these plug-in units, only plug-in unit 3 is shown.

The plug-in unit 3 includes an address converter 41 which is both connected via the address bus 9 to the signal collector 10 and connected to the address-setting device 4 of the plug-in unit 3. The own address is set in the same way as in the switching arrangement according to Fig. 4 or 6. The address comparator 41 compares the plug unit's own address with the addresses given to the address bus 9 of the signal collector 10 in cyclic order. If the addresses are found to be the same, the address converter 41 outputs the equalization signal to the component of the memory component 30. insa 11 to terminal 303 and s i i r t orek i st er in 39 to transfer input S and charge input L.

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The data output D1 of the memory component 30 is fed to the input 3D of the non-driver 39 and its data output D2 is connected to the data bus 5a coming from the signal collector 1. The clock input T of the memory component 30 is connected to a clock conductor 6 common to all plug-in circuits of the non-soundable unit.

The input 3D of the transfer racket 39, for example type 74 HC 165, is connected to the data output D1 of the memory component. Other inputs 2D receive error messages from the error generator F as parallel information.

When Joe the signal collector 10 calls the shift register, there are error messages, the shift register sends a message to the signal collector 10 via the controller 38a, by which the error messages of the error message generator F follow the identification information of the memory component 30 in serial form.

The switching arrangement shown in Figure 7 is most preferably formed as an integrated circuit.

If only error messages have to be read in this case, the signal collector, according to Fig. 8, gives the data line 6 as many clock pulses when there are inputs in the shift register. The data line 5a leading to the data input D2 of the EEPROM remains signalless. The controller 38a issues error messages to the data line 1b 5b.

The reading of the error messages and identification information is shown in Fig. 9. The signal collector gives a relatively long position to the clock wire 6. In addition, the data input D2 of the EEPROM 30 receives a weave message from the signal collector consisting of the read code LC and the address Ad. This causes the EEPROM to output a string with two padding bytes FB, a transport policy but unused address AD, the identification information containing the characters Z1 ... Zn, and the check field SF. The parity bits at the end of the characters Z1 ... Zn are marked with the letter P.

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The controller 38a of Figure 7 first issues error messages FM and then said string from the EEPROM.

Fig. 10 shows a memory component 30, the supply voltage Vpp of which is derived from the clock pulses coming by the clock conductor 6.

The common clock wire 6 passing the signal collectors to the memory components is led to the clock pulse by a diode 61 connected in the forward direction to the supply voltage state Vpp of the memory component 30. There is a capacitor 62 between the supply voltage input Vpp and ground.

The switching arrangement takes advantage of the fact that in both synchronous transmission methods according to which the switching arrangements of Figures 3, 4, 6 and 7 operate, the clock signal is continuously on a common clock conductor 6. A clock consisting of a saccharide pulse train with a frequency of up to 100 kHz is smoothed by a capacitor in the range of about 1 to 10 μF. The amplitude of the ke pulses is about 5V. A smoothed voltage in the range of 3 ... 5V supplies the memory component during its active state, te. while writing or reading. The power consumption of the CMOS memory component 30 is about 2 mA.

The switching arrangement according to Fig. 10 is particularly advantageous in those cases where the switching arrangement for collecting self-monitoring information includes push-in units to which no supply voltage is applied and where connection to the supply voltage is obviously not possible or causes relatively high costs.

Figure 11 shows a memory component 30, the supply voltage input VDD of which is connected directly to the call line 8. If the memory component 30 is selected via its call line 8, this call line has a voltage. This voltage is dimensioned so that it can supply the CMOS memory component 8.

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The periodic block verification method known per se or the generation of a checksum is most preferably used to verify the identification data. In both methods, your programming, which can be a service terminal or a personal computer, calculates the inspection data at the test site when writing the identification data to the EEPROM.

To check the data, a parity bit and a block check field are used, which are stored together with the identification data in the EEPROM. From address 0, the credentials are initially entered. This is followed by a check field, which may comprise 1 or 2 bytes. For identification data, a 7-bit code or an ASCII code according to DIN 66003 is most preferably used, and a parity bit is associated with each character.

The last two bytes following the identification data of the EEPROM belong to the check field. Within this field, when programming, the ID data is calculated using a generator polynomial. This calculation is performed by the programming device.

If the identification data consisting of the 7-bit set code and the parity bit is read with the block check field from the signal collector 10, the same calculation that was also performed when writing to the check field is performed again and the result is compared with the received block check field. If the result does not match the block check field, either a transmission error or a data error occurs in the EEPROM. Transmission errors can be corrected by re-reading the data. EEPROM data errors are reported to the data processing device DVA.

Another advantageous form of data verification involves summing the credentials into parity bits. The 8-bit wide checksum thus obtained is stored at the end of the data block 14 in the EEPROM. The most significant bits of the checksum that no longer fit the length of the word are ignored. When the signal collector 10 later reads the identification data, the parity bit is checked, added to the data bytes, and the checksum calculated in the signal collector is compared with the received one. When an error is detected, the data is read again.

Claims (9)

A method for collecting self-monitoring information in electronic communication technology transmission devices comprising push-in units, at least some of which include monitoring devices having self-monitoring information output devices, wherein the information output devices are connected to the signal collectors (10); characterized in that the identifier memories are component memory components of the EEPROMs (30) comprising a serial data input and a serial data output and are interrogated by the signal collector (10) in an address-selective and clock-controlled manner, and that the signal collector (10) contains device identifiers for a selected and clock-controlled cyclic reading and for an old-new comparison of the received identification data of the device, which device cycles after the first message, only when the identification data changes, identification data is provided to the central monitoring device (data processing device 14). Switching arrangement for carrying out the method according to claim 1, characterized in that the clock inputs (SCL), serial data inputs (301) and serial data outputs (301) of the memory components (30) are connected to the respective signal collector via bus conductors (51 ... 54). (10). Switching arrangement according to Claim 1 or 2, characterized in that the memory component (30) has connections (AO, AI) for enabling the component, which can be connected to the activation potential (ground) per unit or socket and that the EEPROMs (30) can be called in series. with addresses to be transmitted via data lines (51 ... 54). 16 89222 Switching arrangement according to Claim 1 or 2, characterized in that one connection (AO) of the memory components (30) for each component is connected to its own call line (81 ... 8n). Switching arrangement according to one of Claims 2 to 4, characterized in that the data output of the memory component (30) is derived from its other inputs at one input of a shift register connected to the error message generator (F). Switching arrangement according to one of Claims 1 to 3, characterized in that the memory component has, in addition to the identification data, memory locations for parity bits and / or block check fields. Switching arrangement according to one of Claims 1 to 4, characterized in that the supply voltage input of the memory component (30) is connected via a diode to a clock conductor and is provided with a filter capacitor. *. Switching arrangement according to Claim 2, characterized in that the supply voltage input of the memory component (30) is connected to a call line. Switching arrangement according to one of Claims 2 to 8, characterized in that the plug-in units (3) comprise a device (4) for setting an address and an address comparator (35) connected to this device (4) and an address bus (9) connected to the signal collector (10) and a memory component ( 30) one interface (CS) is connected to the address comparator (41). I? 39222