FI851639A0 - Portzonkontroll. - Google Patents

Portzonkontroll.

Info

Publication number
FI851639A0
FI851639A0 FI851639A FI851639A FI851639A0 FI 851639 A0 FI851639 A0 FI 851639A0 FI 851639 A FI851639 A FI 851639A FI 851639 A FI851639 A FI 851639A FI 851639 A0 FI851639 A0 FI 851639A0
Authority
FI
Finland
Prior art keywords
portzonkontroll
Prior art date
Application number
FI851639A
Other languages
English (en)
Other versions
FI86485B (fi
FI851639L (fi
FI86485C (fi
Inventor
Daniel M Mccarthy
Original Assignee
Honeywell Inf Systems
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Inf Systems filed Critical Honeywell Inf Systems
Publication of FI851639A0 publication Critical patent/FI851639A0/fi
Publication of FI851639L publication Critical patent/FI851639L/fi
Publication of FI86485B publication Critical patent/FI86485B/fi
Application granted granted Critical
Publication of FI86485C publication Critical patent/FI86485C/fi

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
FI851639A 1984-04-27 1985-04-25 Portzonkontroll. FI86485C (fi)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US60476984 1984-04-27
US06/604,769 US4680702A (en) 1984-04-27 1984-04-27 Merge control apparatus for a store into cache of a data processing system

Publications (4)

Publication Number Publication Date
FI851639A0 true FI851639A0 (fi) 1985-04-25
FI851639L FI851639L (fi) 1985-10-28
FI86485B FI86485B (fi) 1992-05-15
FI86485C FI86485C (fi) 1992-08-25

Family

ID=24420958

Family Applications (1)

Application Number Title Priority Date Filing Date
FI851639A FI86485C (fi) 1984-04-27 1985-04-25 Portzonkontroll.

Country Status (6)

Country Link
US (1) US4680702A (fi)
EP (1) EP0159713B1 (fi)
AU (1) AU578681B2 (fi)
CA (1) CA1234639A (fi)
DE (1) DE3581826D1 (fi)
FI (1) FI86485C (fi)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4896259A (en) * 1984-09-07 1990-01-23 International Business Machines Corporation Apparatus for storing modifying data prior to selectively storing data to be modified into a register
US4899275A (en) * 1985-02-22 1990-02-06 Intergraph Corporation Cache-MMU system
US5255384A (en) * 1985-02-22 1993-10-19 Intergraph Corporation Memory address translation system having modifiable and non-modifiable translation mechanisms
US4933835A (en) * 1985-02-22 1990-06-12 Intergraph Corporation Apparatus for maintaining consistency of a cache memory with a primary memory
US4884197A (en) * 1985-02-22 1989-11-28 Intergraph Corporation Method and apparatus for addressing a cache memory
US4860192A (en) * 1985-02-22 1989-08-22 Intergraph Corporation Quadword boundary cache system
US5091846A (en) * 1986-10-03 1992-02-25 Intergraph Corporation Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency
US5095424A (en) * 1986-10-17 1992-03-10 Amdahl Corporation Computer system architecture implementing split instruction and operand cache line-pair-state management
US5155833A (en) * 1987-05-11 1992-10-13 At&T Bell Laboratories Multi-purpose cache memory selectively addressable either as a boot memory or as a cache memory
US5168560A (en) * 1987-05-29 1992-12-01 Amdahl Corporation Microprocessor system private split cache tag stores with the system tag store having a different validity bit for the same data line
US5420994A (en) * 1990-08-06 1995-05-30 Ncr Corp. Method for reading a multiple byte data element in a memory system with at least one cache and a main memory
US5357622A (en) * 1990-09-27 1994-10-18 Dell U.S.A., L.P. Apparatus for queing and storing data writes into valid word patterns
US5530835A (en) * 1991-09-18 1996-06-25 Ncr Corporation Computer memory data merging technique for computers with write-back caches
US5491811A (en) 1992-04-20 1996-02-13 International Business Machines Corporation Cache system using mask bits to recorder the sequences for transfers of data through cache to system memory
US5535360A (en) * 1994-08-31 1996-07-09 Vlsi Technology, Inc. Digital computer system having an improved direct-mapped cache controller (with flag modification) for a CPU with address pipelining and method therefor
US6131152A (en) * 1996-05-15 2000-10-10 Philips Electronics North America Corporation Planar cache layout and instruction stream therefor
US6321303B1 (en) 1999-03-18 2001-11-20 International Business Machines Corporation Dynamically modifying queued transactions in a cache memory system
US6311254B1 (en) 1999-03-18 2001-10-30 International Business Machines Corporation Multiple store miss handling in a cache memory memory system
US6269427B1 (en) 1999-03-18 2001-07-31 International Business Machines Corporation Multiple load miss handling in a cache memory system
US6629168B1 (en) * 2000-06-15 2003-09-30 Hewlett-Packard Development Company, Lp. Byte-swapping for efficient use of memory

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5226124A (en) * 1975-08-22 1977-02-26 Fujitsu Ltd Buffer memory control unit
US4084234A (en) * 1977-02-17 1978-04-11 Honeywell Information Systems Inc. Cache write capacity
US4157586A (en) * 1977-05-05 1979-06-05 International Business Machines Corporation Technique for performing partial stores in store-thru memory configuration
US4287561A (en) * 1978-03-16 1981-09-01 International Business Machines Corporation Address formulation interlock mechanism
US4217640A (en) * 1978-12-11 1980-08-12 Honeywell Information Systems Inc. Cache unit with transit block buffer apparatus
US4298929A (en) * 1979-01-26 1981-11-03 International Business Machines Corporation Integrated multilevel storage hierarchy for a data processing system with improved channel to memory write capability
JPS6019809B2 (ja) * 1979-12-26 1985-05-18 株式会社日立製作所 デ−タ処理装置
JPS57105879A (en) * 1980-12-23 1982-07-01 Hitachi Ltd Control system for storage device
US4392201A (en) * 1980-12-31 1983-07-05 Honeywell Information Systems Inc. Diagnostic subsystem for a cache memory
US4499539A (en) * 1982-12-20 1985-02-12 International Business Machines Corporation Method and apparatus for limiting allocated data-storage space in a data-storage unit
US4527238A (en) * 1983-02-28 1985-07-02 Honeywell Information Systems Inc. Cache with independent addressable data and directory arrays

Also Published As

Publication number Publication date
EP0159713B1 (en) 1991-02-27
EP0159713A2 (en) 1985-10-30
FI86485B (fi) 1992-05-15
AU578681B2 (en) 1988-11-03
FI851639L (fi) 1985-10-28
AU4173485A (en) 1985-10-31
US4680702A (en) 1987-07-14
DE3581826D1 (de) 1991-04-04
CA1234639A (en) 1988-03-29
FI86485C (fi) 1992-08-25
EP0159713A3 (en) 1987-07-29

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Legal Events

Date Code Title Description
MM Patent lapsed
MM Patent lapsed

Owner name: HONEYWELL INFORMATION SYSTEMS INC.