FI810807A - Anordning foer temporal oeverlappning av skriv- och laesoperationer i minnet av en synkroniserande apparatur - Google Patents

Anordning foer temporal oeverlappning av skriv- och laesoperationer i minnet av en synkroniserande apparatur

Info

Publication number
FI810807A
FI810807A FI810807A FI810807A FI810807A FI 810807 A FI810807 A FI 810807A FI 810807 A FI810807 A FI 810807A FI 810807 A FI810807 A FI 810807A FI 810807 A FI810807 A FI 810807A
Authority
FI
Finland
Prior art keywords
synkroniserande
skriv
oeverlappning
laesoperationer
minnet
Prior art date
Application number
FI810807A
Other languages
English (en)
Finnish (fi)
Inventor
Georges Thiebaut
Original Assignee
Cit Alcatel
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cit Alcatel filed Critical Cit Alcatel
Publication of FI810807A publication Critical patent/FI810807A/fi

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/05—Electric or magnetic storage of signals before transmitting or retransmitting for changing the transmission rate
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
FI810807A 1980-03-21 1981-03-16 Anordning foer temporal oeverlappning av skriv- och laesoperationer i minnet av en synkroniserande apparatur FI810807A (fi)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8006353A FR2478860A1 (fr) 1980-03-21 1980-03-21 Dispositif d'imbrication des ecritures et des lectures d'informations dans une memoire

Publications (1)

Publication Number Publication Date
FI810807A true FI810807A (fi) 1981-09-22

Family

ID=9239950

Family Applications (1)

Application Number Title Priority Date Filing Date
FI810807A FI810807A (fi) 1980-03-21 1981-03-16 Anordning foer temporal oeverlappning av skriv- och laesoperationer i minnet av en synkroniserande apparatur

Country Status (6)

Country Link
EP (1) EP0036596A1 (ja)
JP (1) JPS56147538A (ja)
FI (1) FI810807A (ja)
FR (1) FR2478860A1 (ja)
PL (1) PL230228A1 (ja)
RO (1) RO84258B (ja)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3809820A (en) * 1973-04-03 1974-05-07 Us Navy Multi-channel asynchronous to synchronous converter
FR2256606B1 (ja) * 1973-12-27 1978-02-10 Roche Alain
FR2363947A1 (fr) * 1976-09-02 1978-03-31 Roche Alain Equipements de raccordement entre des systemes de transmission numerique multiplex a modulation par impulsions et codage mic a debits binaires nominaux differents
US4056851A (en) * 1976-09-20 1977-11-01 Rca Corporation Elastic buffer for serial data
US4158107A (en) * 1978-01-23 1979-06-12 Rockwell International Corporation Integral frame slip circuit

Also Published As

Publication number Publication date
FR2478860A1 (fr) 1981-09-25
FR2478860B1 (ja) 1984-07-20
PL230228A1 (ja) 1981-11-27
RO84258A (ro) 1984-05-23
JPS56147538A (en) 1981-11-16
RO84258B (ro) 1984-07-30
EP0036596A1 (fr) 1981-09-30

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Owner name: COMPAGNIE INDUSTRIELLE DES