FI71623C - ASSOCIATIVT MINNE. - Google Patents

Description

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ASSOCIATED MEMORY

The invention relates to an electronically implemented network-like associative memory.

Associative memories are discussed in Science 2000, issue 2/1980. Pre-known memories are as follows: 1. Memories in which information is stored in a specific memory location, from which information is then retrieved using a decoder, lookup table, logical or mathematical search comparison methods (e.g., a correlation function).

These memories are more or less devices based on a computer program or a search procedure, mainly suitable for sorting data.

2. Memories in which information is distributed around the memory by mathematical methods. In these, it is possible to store data in memory locations on top of each other and to find data with very incomplete key information. The difficulty with this method is also program-based and mathematical operations, which result in large and slow hardware.

3. Memories in which key information is compared with information in memory piece by piece or bit by bit (e.g., with sum streams: matching similar bits or pieces increase but different subtract the total current). This way, for example, words like search information can be found quite easily, but the words must be in place. The offset or elongation of any piece or bit can take the whole comparison wrong. The internal structure of the information is not properly taken into account either. Overall, the method is relatively limited even due to its rigid structure.

In addition, all the types of memory listed above have the weakness of trying to store the data as it is and extract it again in a photographic manner. This procedure results in a large need for memory capacity, since even data with a large amount of information in itself but a small amount of subscription information (relationships) with other data are stored as such.

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In addition, are known so-called. programmable logic logs. The way they are constructed and programmed (on / off) and the way the signal is processed is therefore rudimentary that they are not considered associative memories.

Mathematical and program-based analysis methods do exist, but a properly functioning linear, logic-based analysis method does not, for some reason, be popular in associative memories, although it is a fast and efficient method to overcome the difficulties described above. The method according to the invention takes this into account. The invention is characterized by what is set forth in the characterizing part of claim 1.

The following can be considered as the main advantages of the invention. The computer-like program for data processing has been abandoned. Likewise, information is not modified using mathematical methods. The information is processed in a straightforward, comprehensive manner and only what is necessary at the time (e.g., dependencies and influences) is stored. These measures increase memory speed and efficiency. The stored data is distributed around the memory, so that several different data can overlap in one memory location. The stored information is now highlighted even with significantly incomplete key information. The internal structure of the information, as well as additional or environmental information at the same time, will also be taken into account. Operational accuracy is achieved - not as the sum of individual precise functions - but as a statistical event. In terms of memory capacity, there are excellent prospects, as the decisive factor is now the number of route combinations and not the number of memory locations.

In the following, the invention will be described in detail with reference to the accompanying drawings.

Figure 1 shows the structure of one unit.

Figure 2 shows the principle of interconnection of units. Figure 3 shows an arrangement for letter recognition.

Figure 4 shows a block diagram of associative memory.

Figure 5 shows a flow chart of associative memory.

Il 3 71623 The memory elements used, at least some of which must be non-volatile (RAM), are grouped either physically or (and) addressably, depending on the solution chosen. The unit consists of: 1) A signal memory (e.g. θ-bit), the current value of which depends on the signals coming to the unit and which varies even if no data is stored in the associative memory. This part of the unit is always of the read-write type (RAM) · 2) Switching memories (e.g. 4-bit) whose memory content determines the signal amplifiers by controlling the way or strength of the signal from the unit affects the signal memories of other units. The contents of the memory can only change to associative memory when writing data. It should be noted that in the storage phase, usually only in some units the contents of the switching memories change. In addition, the unit may have 3) directional memories (e.g. 2x4 bits), the contents of which ("telephone number t M) define the signal path selectors by controlling which units are affected by the signal memory of the po.

This information can also be the same for several or even all units, e.g. "all neighboring units", in which case the direction information can be partially or completely located outside the unit, e.g. in some counter. This part can also be used in the recording phase - like the switching part - albeit to a more limited extent. Due to their structure, the units now allow them to be connected to a single network by means of suitable auxiliary circuits.

In the solution shown in Figure 4, the memories of the units are grouped into three parts as described above. This solution deals with only one unit at a time and the effect of this signal on only one unit at a time.

Therefore, a unit and switching counter is used, and identical memory parts (e.g., signal parts) of different units may be located physically close to each other, even in the same microcircuit from which they are addressed in an address if necessary. A further advantage of this solution is that the necessary auxiliary circuits are now common to all units. When looking at each unit, the unit counter assigns an address to the direction and switching memory blocks, whereby the direction and switching parts belonging to the unit appear according to the subaddress of the switching 4 71623 counter (i.e., the one that indicates how many switching relationships are currently being viewed).

The address also goes from the unit counter to the address adder, i.e. the directional memory only gives a relative address. This need not be the case, but the directional memory may directly contain the absolute address at which the signal memories of the units of the switching relationship under consideration can be found. The initial setting from the switching counter to the address adder has been used because it is easy to move from one unit layer to another, as well as to go backwards in the width and length direction without subtracting the addresses (Figure 2).

Referring to Figure 4, Figure 5 is a corresponding flow diagram showing the coupling of one unit to lower units in the hierarchy. At the beginning of the cycle, the contents of the unit's signal memory are entered into the A register. The export takes place via a limiter which can control the degree of operation or sensitivity and which prevents weak signals from advancing so that they do not clutter the paths of the respective main signals. If the zero indicator indicates that the limiter output is zero, the next unit is moved to win the time. The magnitude of the signals is represented as a parallel binary number. When the signal memory information is in register A, the first unit affected by this information is displayed. To do this, the first directional part is introduced into the address adder. The contents of register A are summed in the signal memory now to be displayed as indicated by the switching part belonging to the directional part. If the switching part indicates that it is a blocking signal, the signal memory is reset or set so that it cannot be changed by other units in this cycle. Of course, the switching part can also tell that the signal is summed as negative in the signal memory. A latch register is needed for RAM usage reasons (to prevent an immediate connection from output to input at the write stage). By moving the switching counter, the next directional part is then taken, which is fed to the address adder, and the second signal memory that appears is done as for the first one. In this way, all the directional and coupling parts of the present unit are passed through in pairs.

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When one unit is completed, the next one is moved by moving the unit counter forward and the processing cycle described above is repeated. This goes through all the units, after which we go back to the beginning. Activities continue from round to round over and over again.

As a result of the above operation, signal paths are formed through the associative memory from top to bottom. The paths are determined on the one hand by the switching parts (and of course the direction parts) of the units and on the other hand by the signals coming to the first unit layer. The transmission of signals through the network takes place in such a way that sufficiently strong signals entering the surface layer (memory input) affect the units of the next layer along certain paths. Each route has its own weight. When enough signals arrive at one of the second (or other) layer units (the weaker, the more they are needed), the unit outputs the signal. Thus, the input signals provide parallel signal paths passing through the memory. Signals can also move from one unit to another laterally, allowing them to sensitize (or prevent) adjacent units on the same layer.

If, then, the incoming signals are not random but form a certain pattern, the consequence is that the very units and paths on which the incoming signals are concentrated according to their pattern and the weight of the connections between the units are activated. That is, the incoming signal pattern provides a predetermined path pattern and thus also a predetermined output pattern to the memory output. This is also the case when the input pattern is “new” to the memory, but especially when the route pattern is strengthened or amplified (weighted or grooved) for this pattern. The more discrete and accentuated the route pattern, the more incomplete the input pattern will be able to provide the correct output pattern. The absence of some signals does not matter - the number and pattern are decisive. This is the essence of associative action.

By appropriately selecting the switching parts for each set of signal signals, a desired or identifiable set of output signals is obtained.

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The signal limiter as well as the signal amplifier (and also the summers) can simply be PROM circuits programmed according to the desired transformation, the addresses of which are variables and the output is the value of the function. Of course, the computational solution works, but it is slower. Regarding the operating speed of the memory, it should be mentioned that it takes about 1 ms to recognize a single letter and enter its ASCII code using a 2 MHz clock frequency and a 16x16 unit raster.

In the solution described above, parallel digital signals were used, but the device also works equally when analog signals or serial digital signals are used.

It should be noted that this device is only the basis and, in addition, suitable programming is required for each application, as is the case with conventional computers. The machine is also made to program itself using suitable accessories or additional programs in computer simulation. The programming of switching memories is a one-time event, because once programmed memories also function as such on other machines performing the same task.

Various methods are available for programming associative memory.

1. When the output pattern corresponding to the input pattern is known, the patterns of the possible intermediate layers are first constructed so that the input pattern converges through them towards the output pattern. The memory is then grooved so that two consecutive patterns are taken, and the switching memories of the directional memories that connect the points of the patterns are weighted.

2. Where the output pattern is not known in advance but can be given meaning only at a later stage, the procedure shall be such that the input pattern itself determines the type of intermediate and output patterns to be created and the grooving is then made as in point 1.

However, even if a new pattern is so similar to an earlier one that the risk of mixing is obvious, one of the two patterns can be moved by adding a guiding pattern (but not grooved) to the upper pattern and then proceeding according to step 1. In this way, patterns are obtained in their own sufficiently large compartments. The range of motion required by the patterns depends on the total number and quality of the patterns and the incompleteness of the input patterns. The sufficiency of the spaces should be determined by experimenting »thus by changing the input patterns and increasing the space of movement, if necessary, as described above.

Steps 1 and 2 can be done as a computer simulation, in which case a separate program is needed to record the routes and change the associated weights. Associative memory programming can also be done with the device itself, as long as it is slightly modified. Units that exceed the trigger threshold (limiter output ^ 0) are not reset, and when a second-to-second connection occurs between two such units, the corresponding weighting (switching memory) is changed so that the route effect increases.

3. In addition, evolution-type programming can be used. In this case, those changes in the program that contribute to the achievement of one of the goals are accepted, or more broadly: those that are disadvantaged are rejected. So this is experimental programming.

In support of associative memory, it is sometimes advisable to use registers in which previous or newly implemented instructions are stored. Some of the output signal sets may be operating instructions or the like, e.g. instructions for replenishing the input signal set.

The machine is quite useful in various identification tasks (letters, words, patterns, sounds, etc.) where fast and good regenerative ability is required. All kinds of observational tasks are also in the field of machines.

It is conceivable that several machines operating in parallel and cooperating with each other are placed in one microcircuit. This will increase the efficiency and start approaching the functioning of the human brain.

Claims (9)

71623 1. An electronically implemented network-like associative memory characterized in that units are grouped from the respective memory elements so that each has a continuous-written signal memory, directional memories and switching memories, the signal memory of which indicates the current state of the unit when the associative memory is operating and the unit the programmed directional memories in the unit are controlled by the signal paths of the unit, whereby the signal memory of the unit can affect the signal memories of the units to which the unit is connected via a weak signal suppressor, as determined by the signal amplifiers in the unit. by steering (Figures 1 and 2). The associative memory according to claim 1, characterized in that the signal flow between the signal memories can also take place in the opposite direction, i.e. from the signal memories of the units to which the unit is connected to the signal memory of the connected unit. Device according to Claim 1 or 2, characterized in that it has a unit counter for checking only one or a few units at a time and / or a switching counter for checking one or more switching ratios at a time, the necessary auxiliary circuits, such as signal sum , the signal limiter, signal amplifiers and routers are at least partially shared by all or several units, and the grouping of memory items can be done at least in part by grouping the addresses of the items (Figure 4). Device according to one of the preceding claims, characterized in that it has a counter for controlling the coupling of the units to each other at least partially from outside the units or the units are fixedly wired together, in which case the units do not necessarily need orientations. 9 71 623 Device according to one of the preceding claims, characterized in that it has units which can give a signal which prevents or tends to prevent the operation of a unit to which said the unit turns on. Device according to one of the preceding claims, characterized in that the unit-specific memory not only controls the signal strength in addition to the signal strength. Device according to one of the preceding claims, characterized in that the signal is also switched to a higher level in the hierarchy, such as from the output of the associative memory back to the memory input. Θ. Device according to one of the preceding claims, characterized in that a signal limiter is used as the signal amplifier or vice versa. Device according to one of the preceding claims, characterized in that the input signal collectors, the output signal limiters or the signal amplifiers can be adjusted according to the function, such as the total number of signal paths. Device according to one of the preceding claims, characterized in that the units are grouped for certain tasks, acting either independently or independently, and the groups in turn form an associative memory of the operations. 71 623 PATENT LOAD