FI69375B - FOER REFRIGERATION FOR INTEGRATING AV INTEGRATED SCREENS AV MOS-TYPE - Google Patents

Description

69375

Method for manufacturing MOS-type integrated circuits

A method for manufacturing MOS-type integrated circuits 5, in which the circuits are formed by monolithic techniques with processing steps known per se.

The most significant integrated circuit manufacturing technique is the monolithic technique used to fabricate almost all circuits with a high degree of integration (LSI, VLSI). A key part of the monolithic technique is the planar process, the main steps of which consist of coating the silicon wafer with an oxide, into which, by mask technique, resistors and etchings, windows corresponding to the desired surface pattern are made, from which the alloys are diffused from gas or ion-implanted.

Metal oxide semiconductors (MOS) offer numerous possibilities for the implementation of various logic forms and are particularly well suited for integration with monolithic technology, especially in LSI and VLSI circuits. This is due to their simple structure and small space requirement compared to e.g. bipolar transistors. Over time, various versions of monolithic integration of MOS circuits have been developed, such as metal lattice MOS and 25 silicon lattice MOS processes, complementary MOS process (CMOS), and various variations of these.

Metal lattice MOS is the oldest and simplest process. However, it is relatively slow, and as a family of logic rare. The advantages of the Silicon Gate MOS (Silicon Gate MOS) process-30 process include small size and high speed. Both metal and silicon MOS circuits can be either N-channel (NMOS) or P-channel (PMOS). Complementary Metal-Oxide-Semiconductor (CMOS) circuits, which are well suited for Paris-powered devices, have both N- and β-channel transistors on the same substrate. The mono-69375 connector technique typically starts from a n-type silicon wafer into which relatively deep p-type pools are diffused, into which N-channel transistors are generated, while β-channel transistors are generated directly on the n-substrate. The CMOS process offers the advantages of very low power consumption, good interference immunity and a wide operating voltage range.

In the manufacture of a type of MOSFET transistor, a Surface or Insulated Gate Field Effect Transistor 10, known masking techniques are used to generate the source and drain regions S and D (Source and Drain) close to each other on the surface of the semiconductor. The regions are generated either by implantation of high energy ions or by gas phase diffusion.

15 A thin, high-quality insulating film is created on the surface of the channel area, e.g. by thermal oxidation, and a gate covering the entire channel from the material leading to it.

Typically, the channel region is poorly conductive and has the opposite conductivity type to the source and drain regions. By applying a voltage in a suitable direction to the lattice, a thin inversion film is generated on the surface of the channel area, whereby e.g. a p-type channel changes to an n-type surface, forming an n-channel between n + -type S- and D-regions.

-f -f - - 25 The notations n, p, n, p, n, p are self-explanatory notations for semiconductor dopant concentrations for those skilled in the art and are not explained in more detail herein. If necessary, any textbook in the field will provide an explanation of the terms. As technology advances, the length of the channel 30, i.e. the distance between the S and D regions, has been continuously reduced to less than 1 μm (micrometer). In this case, the discharge regions generated below the inversion layer and over the pn interface separating the D-region from the bottom region interfere with the operation of the transistor more than when the channel 35 is relatively long. These disturbances are called short-channel phenomena.

This invention relates to a new type of surface channel transistor in which the above-mentioned perturbations are eliminated. To achieve this effect, the method according to the invention is mainly characterized in that an insulating groove is created under the channel area of the MOS transistor, on which a thin polycrystalline semiconductor film is grown so as to at least partially cover the intended source and pharyngeal regions, after which the semiconductor film is melted locally. with a laser beam or other purpose-appropriate heating device and allowed to cool at the insulating groove to the same single crystal as the source and drain zones.

The invention differs from known methods in which an amorphous silicon film grown on an insulator becomes polycrystalline in heat treatment. The electrical properties of the monocrystalline material 15 are known to be superior to polycrystalline. By controlling the thickness, conductivity type and conductivity of the semiconductor film in the channel region, the electrical properties of the channel transistor, such as the threshold voltage, determined by it can be easily and flexibly controlled. At the same time, the drain-subtrate capacitances decrease, making the circuit suitable for high operating frequencies. The transistor can be made an enhancement type: normally-off or a depletion type: normally-on.

A preferred embodiment of the method according to the invention is characterized in that said channel groove is formed and filled with oxide at the same time as the insulating grooves separating the elements of the circuit.

This makes manufacturing relatively easy and 30 economical. In integrated circuits, elements, i.e. transistors, diodes, resistors and capacitors, are electrically separated from each other mainly by two different basic methods: a) at the pn interface, which is usually in the blocking direction, 35 b) by different dielectric methods in which the elements are separated by an insulator film, groove, wall, etc.

This embodiment of the invention is particularly suitable for those variations in which the semiconductor 5 is reacted, for example, by reactive ion etching.

Etching) creates narrow rectangular grooves that are filled with either thermal or chemical vapor deposition silica or other insulating material. The grooves 10 filled with insulation are typically deeper than the diffusion depths used to generate the elements. In this case, the pn interfaces end in an insulating groove, which has been found to result in positive rather than negative properties in the electrical operation of the elements.

A preferred embodiment of the method according to the invention is characterized in that the semiconductor film alone is excited to form the source and drain regions of the circuit. This solution saves work steps because the source and drain regions do not have to be formed separately for the substrate.

A preferred embodiment of the method according to the invention is characterized in that the semiconductor film is processed in such a way that electrical connections or silicon oxide insulation, respectively, are formed between the various elements of the circuit. In this case, e.g. in integrated circuits, the very common parallel connection of transistors to complement pairs can be carried out without additional conductors, only a suitable doping of the semiconductor film is sufficient for this purpose.

Other preferred embodiments of the method according to the invention are characterized by what is stated in the claims below.

The invention will now be described in more detail by way of example with reference to the accompanying drawing, in which Figure 1 shows a finished surface channel transistor 5 69375 made according to the prior art, Figures 2a-2f show manufacturing steps of a surface channel transistor according to the invention. in the final stages of the manufacturing process, Figure 4 shows a circuit diagram of the finished CMOS circuit. Figure 1 shows a typical self-aligning silicon lattice PMOS surface channel transistor. It is processed on a 10-type substrate 4 by first growing an insulating oxide film 9 covering the entire silicon wafer, etched from the regions of the intended transistors. Thereafter, a thin oxide film 7 and possibly also a thin nitride film (Si Next, the oxide film 7, the nitride film 8 and the silicon film are etched away except from the area of the desired lattice 2. P + -type alu-20 eet 5 and 6 have been diffused into the formed oxide windows on both sides of the lattice 2. At the same time, the lattice film 2 strongly mixes and becomes very conductive. Next, an oxide film 10 is formed over the entire circuit, and formed by etching the windows on the source and drain contacts 1 and 3. Finally, a metal film such as aluminum 25 is generated, e.g., by evaporation.

In the CMOS manufacturing process according to the invention of Fig. 2, the starting material is a monocrystalline silicon wafer 11 with a lattice index-30 direction in the (100) direction and a surface resistance of 1 to 2Q ohmcm p-type. It is initially coated according to Fig. 2a. according to the oxide layer 12, after which n-pools 13 are formed on certain surface portions 35 of the disc 11 using planar process methods. The dopant may be formed of As, Sb or P "doping" atoms. Of course, the starting material 69375 can also be of the n-type, in which case the generated pool is of the p-type. The structure may also be epitaxial.

According to Figure 2b, a mask is created from the photoresist 5 14 on the surface of the silicon, with openings in them at the point where it is desired to etch the insulating grooves 15. The etching can take place, for example, by the RIE (Reactive Ion Etching) method to the desired depth. The same photoresist mask 14 and etching are also used in the invention to create a lattice groove 16 having an essential part 10 and to chemically fill the grooves 15, 16 with silica by known oxidation methods. Thermal oxidation can also be used, it is important that the surfaces of the silica in the grooves and the surrounding silicon regions are at least approximately in the same plane. In this connection, stimulator areas 32 ns can also be created at the bottom of the grooves to prevent the formation of parasitic channels (see Fig. 3).

According to the known methods, new photo-20 resist masks can now be generated in two successive steps according to Fig. 2c on the surface of the p-substrate n + -type S / D regions 18 of the N-channel transistors and p + -type transistors of the n-pools 13 S / D Areas 19. Figure 2c shows the situation after both steps, before removing the second mask 17.

25 It should be noted that masking is not critical but may extend in part over the insulation grooves. The step described above can also be omitted in some cases (see Fig. 3).

Over the whole disc is now grown very thin 0.1 ...

30 .mu.m thick p-type silicon film 20 e.g. by CVD method or sputtering (Fig. 2d). The normal method masks the silicon film away from non-active areas, i.e. the transistors, etc., and crystallizes both the channel areas 21 and 22 and the other desired parts of the silicon film into one-35 crystals according to the invention, e.g. by means of a laser beam.

Il 69375

Instead of a laser, it is possible to use hot strip technology or an isothermal reaction with a surface heating lamp. The S / D regions act as seed crystals in the crystallization. Thereafter, using masking 23 and ion implantation, the intended n-channel regions 21 are "boosted" to the opposite type to the p-type S / D regions 19 of the transistor, e.g., with phosphor. The P-channel area 22 is already of the correct type. Figure 2d shows this situation. The grown silicon film can also be self-conducting (intrinsinc), in which case its channel region-1Q portions must be excited to the p- or n-type, depending on the type of transistors desired. If the polycrystalline silicon film 20 extends over the grooves 15, it can act either as an insulator 20a (e.g., by converting the silicon film to insulating silica by pressure oxidation as shown in Figure 2e), or so-15 n + -type semiconductor), the film can also act as a conductor 20b between two transistors or other circuit elements over the insulating grooves 15, as shown in Fig. 20 2f. N + and p + tightening of the film 20 is necessary when the underlying n + and p + regions 19 and 18 have not been formed in the previous step (see Fig. 3).

Then, according to Fig. 2e, a high-purity oxide or other insulating film 25 24 and a conductive film 25 are grown on the surface of the silicon, which later acts as a lattice. If the film 25 is also to be used as a conductor in the S / D regions, the contact openings 31 must be etched into said thin insulating film 24 before it is grown, as shown in Fig. 3. In addition, if block-30 type MOSFETs are desired, the excitation is adjusted so that the source-channel-drain configuration is n-channel and for p- + + + + channel transistors n -nn and p -pp, respectively · The gate metal films 25 used are e.g. polycrystalline silicon, silicides of silicon and several metals, aluminum and other 35 metals.

69375 Thereafter (Fig. 2f) the conductive film 25 is masked so that it remains only in the desired areas as a lattice, buried contacts and conductors. After masking, ion implants can be performed, in which transis-5 markets become so-called self-aligning, but this is not necessary. The circuit elements are then processed in a known manner, coated with protective layers, e.g. CVD oxide 26, in which the contact openings are masked, after which one or more conductor films are grown, contacts 27, 28, 29 are formed and passivated with a protective film 30. Figure 2f shows an example final CMOS of an inverter circuit in which the source regions of the p-channel transistor and the drain regions of the n-channel transistor are connected by a prong 20 and connected to a common contact member 28. It should be noted that e.g. the connection between the gates is not shown in Fig. 2f. Figure 4 shows a corresponding circuit diagram of a CMOS inverter. The correspondences between the poles of Figure 2f and 4 are 25 = IN, 27 = Vgg, 28 = OUT, 29 = VDQ.

It will be apparent to those skilled in the art that the various embodiments of the invention are not limited to the above example, but may vary within the scope of the claims set forth below. Thus, the method of the invention can be applied to channel formation and modification of its properties in any MOS-type semiconductor manufactured primarily by the monolithic technique. The more precise manner and order of implementation of the various manufacturing steps may also vary. For example, instead of a laser, an epitaxially grown polycrystalline silicon layer can also be crystallized with a moving 3Q heating tape.

li

Claims (8)

1. A method for manufacturing integrated circuits of the MOS type, in which the process circuits are formed by monolithic technology during the process chain known per se, characterized in that an isolation barrier (16) is provided under the channel area (21) of the MOS transistor. on which a thin polycrystalline semiconductor layer (20) is formed such that it at least partially covers also the intended emitter and collector regions (18, 19), after which the semiconductor layer (20) is fused locally with laser beam or other for the purpose. suitable heating device and allowed to cool at the insulation barrier to the same monocrystal as the source electrode and outlet electrode regions. 15 2. A method according to claim 1, characterized in that the channel latch (16) is formed and filled with oxide at the same time as the isolation latches (15) which separate the various elements of the circuit. A method according to claim 1 or 2, wherein the semiconductor layer (20) is formed by an epitaxial method, characterized in that the crystallization of the layer is allowed to take place directly in the epireactor. 4. A method according to claim 1, 2 or 3, characterized in that the semiconductor layer (20) is doped to form the emitter and collector areas of the circuit alone. 5. A method according to any of claims 1-4, characterized in that the semiconductor layer (20) is processed, so that electrical connections are formed between the various elements of the circuit. Process according to any one of claims 1-5, characterized in that the semiconductor layer (20) is locally converted to silica.