FI58842B - ANORDNING FOER KLOCKSIGNALDISTRIBUTION - Google Patents

Description

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Patent and the Board of Regents' AmOkan issued without notice * cpft * n published 31.12.80 (32) (33) (31) hn ^ * «ty *« * olk * u »-« * | »rd prtorltut 21.02.75

Ruotsi-Sweden (SE) 7501976-0 (71) Oy LM Ericsson At », 02U20 Jorvas, Suomi-Finland (FI) (72) Carl-Axel Ingemar Roseen, Ludvika, Ruotsi-Sweden (SE) (7 * 0 Oy Kolster The present invention is an apparatus for distributing clock signals of the type in which clock signals are generated by means of a digital counter, driven by an ethereal oscillator.

The specifications for IC circuits indicate the amount of load that the circuit outputs can be exposed to, expressed in the total number of unit charges. Furthermore, it is stated how many unit loads that the different circuits represent, why the cone designer directly for instructions on how signal processing must be applied when distributing a signal to a larger number of asset receiving circuits. The need arises especially often when distributing clock signals in a larger digital system, whereby according to the conventional solution the clock signal source is loaded with a number of drive amplifiers, which in turn can each operate a number of loads. The disadvantage of this solution is that the individual amplifiers give rise to a varying degree of delay of the mediated clock signals *, which becomes particularly noticeable at high clock signal frequencies. This varying delay means that the clock signals will appear with corresponding phase offsets in different parts of the digital system.

2 58842

The clock generates the clock signals using a digital counter, which drives an etyro oscillator. The clock signals can be output directly from the individual counter steps, but most often the counter is followed by a decoder with outputs for specific counter positions. A conceivable measure to achieve a large number of parallel clock signal outputs without introducing further delays beyond those occurring in the counter and the decoder would be to arrange multiple counters in parallel, each with its decoder, where all counters are etched by a common oscillator. However, for such a device to become practically useful, special devices are required to synchronize the counters with each other, so that the counter cycles coincide. The synchronization can, for example, be accessed by means of a device based on the rich patent specification 298077 which comprises a majority decision circuit in connection with each counter as well as circuits for generating set pulses to the counters each time the majority of the counters have changed each in the metetate count. . TWO times in each counting cycle. Late solution thus results in a fairly large component range in relation to each counter, which greatly reduces the reliability, so that A matches only between the metrically significant counter positions. In most cases, however, it is desirable to obtain clock signals on several occasions during the counting cycle, so that all counting positions are equally important. The problem is solved according to the invention in such a way that the control oscillator controls a master counter, from whose outputs control conditions are output to a number of slave counters which are increased by set pulses synchronous with the control oscillator and all slave counters are output from the clock counter,

The invention will now be described by way of example and with reference to the accompanying drawing.

As shown in the drawing, the apparatus according to the example comprises a main counter consisting of two bistable flip-flops FF1, FF2 of the T-type, which are driven by an etyroscillator KL. A T-type flip-flop is provided so that wrapping occurs from the present state to the opposite state, e.g. from 1 to 0, every time a pulse is received at input T. The same etyroscillator also delivers set pulses to a number of slave counters, three of which are shown in the drawing. Like the example in the upper part of the drawing, these counters consist of each two JK-type flip-flops, FF 3 »FF 4 and FF 5, FF 6, respectively, which receive control conditions from the main counter's outputs, which will be described later. A JK-type flip-flop is set by means of an executing pulse on input G to the binary state indicated by activating either input J or input K. According to the embodiment, the device also comprises decoders AK 1, AK 2, which are connected to each slave counter and on whose outputs clock signals are output in beet tame counter pointers.

Further down the drawing, there is also shown an electric counter of an alternative embodiment, namely in the form of a ring counter. This is formed by four D-type flip-flops FF 7 -PP 10, which receive control conditions from a decoder AK 3 connected to the main counter. A D-type flip-flop is provided that it is set by means of set pulses p & ing G in a position determined by the binary etyr condition P & gning D.

The two flip-flops PP 1, PP 2 form a circular 4-counter, which is advanced in step with control pulsed path KP from the control oscillator KL. The outputs U 10, D 11 are then switched on for each control pulse and the outputs U 20, ϋ 21 for each other control pulse, the latter however with some delay depending on the switching time of the flip-flop PF 1. The binary states on the outputs U 10, U 11 , K p & lashes FF 3, PP 5 etc., while the state of p & & 20, U 21 is applied to the inputs J, K p & lashes PP 4 »PP 6 etc .. Therefore, with the occurrence of a clock pulse on the path KP, these states will The p & JK flip-flops will be transmitted, and this transfer will be initiated simultaneously for all electricity calculators. According to the embodiment, the same clock pulse is used as for the operation of the main counter, which is why it is simultaneously advanced to the next counter position and provides control conditions for the next adjustment of the slave counters. As above, the slave counters' switching is initiated at the same time, but due to differences in the components, the switching takes place with different delay in each counter. The difference in turnaround time between TV & slave counter output corresponding to one another, e.g. However, U 30 and IJ 30, through this device, refer to the spread in component data for a single logic step. Of course, additional time differences arise if the signals shown in the slave counters are followed by each of the decoders AK 1, AK 2, etc., which supply clock signals at their outputs KS 1, KS 2 etc. in beet tame counter pointers.

Within the scope of the invention, the device described above can be modified in various ways. The counters can e.g. is made as oak. Möbius counters, which, for divisions above 4, partly require more steps than the binary counters and partly require functional monitoring, but in return have other advantages. Thus, the decoders of the Möbius counters thus become less component demanding, at divisions above 4, and secondly, the oscillator frequency can be increased, because all the counters are clocked and so there is no delay between the individual counts. As a further * 58842 modification, master counters and slave counters can be of different design. By inserting a decoder AK 3 directly after the main counter, as shown in the drawing, the electric counters can thus take the form of ring counters, e.g. FF 7 - FF 10, which has the advantage that the decoded clock signals can be extracted directly from the output of the slave counters, e.g. KS 3, and the e-transmission between the signals becomes unimpressed. However, with this device, the operating frequency high control oscillator cannot be selected as high as the device described by the device, due to the spread caused by the decoder to the high control conditions of the electrical calculators.

Claims (3)

5 58842 Patent Claims 1. Apparatus for distributing clock signals of the type in which clock signals are generated by means of a digital counter powered by a control oscillator, pitched therefrom, to achieve a uniform distribution of the clock signals in phase positions when distributed to a variety of receivers said device comprises a master counter (FF1, FF 2) which drives said control oscillator (KL) and a plurality of electrical counters (FF3, FF 4 * FF 5 »FF6) which are incremented by means of all common slave counters and synchronous set pulses with the control oscillator in accordance with control conditions, most of said master counters have count positions, said clock signals being extracted from the slave counters. 2. Device according to claim 1, characterized in that each of said slave counters comprises the same number of calculator steps as said main counter, said control conditions being taken directly from the individual step outputs in the main counter and supplied to the control inputs at corresponding steps in slave counters. Device according to claim 2, characterized in that said clock signals are output from said slave counter via decoders (AK 1, AK 2). 4. Apparatus according to claim 1, characterized in that at least one of said electric counters (FF 7 "FF 10) is designed as ring counters, whereby for these slave counters said control conditions are supplied from said main counter via decoder (AK 3). corresponding to each decoded calculator step corresponding to the respective slave counters, as other slave counters (FF 3 »FF 4» FF 5 »FF 6) have the same number of calculator steps as the main counter, whereby for the other slave counters the control conditions are taken directly from the individual main calculators. and the controls are added to the corresponding steps in the slave counters. Device according to claim 4, characterized in that said clock signals are taken from said other slave counters via decoders (AK 1, AK 2).