FI20106357A0 - Method and apparatus for an action directed to a portion of an electronic structure - Google Patents

Method and apparatus for an action directed to a portion of an electronic structure

Info

Publication number
FI20106357A0
FI20106357A0 FI20106357A FI20106357A FI20106357A0 FI 20106357 A0 FI20106357 A0 FI 20106357A0 FI 20106357 A FI20106357 A FI 20106357A FI 20106357 A FI20106357 A FI 20106357A FI 20106357 A0 FI20106357 A0 FI 20106357A0
Authority
FI
Finland
Prior art keywords
electronic structure
action directed
directed
action
electronic
Prior art date
Application number
FI20106357A
Other languages
Finnish (fi)
Swedish (sv)
Inventor
Kimmo Jokelainen
Ville Moilanen
Hannu Vasama
Kimmo Maekelae
Ahti Haapalainen
Original Assignee
Valtion Teknillinen
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Valtion Teknillinen filed Critical Valtion Teknillinen
Priority to FI20106357A priority Critical patent/FI20106357A0/en
Publication of FI20106357A0 publication Critical patent/FI20106357A0/en
Priority to PCT/FI2011/051138 priority patent/WO2012085347A1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67242Apparatus for monitoring, sorting or marking
    • H01L21/67294Apparatus for monitoring, sorting or marking using identification means, e.g. labels on substrates or labels on containers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/681Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
FI20106357A 2010-12-21 2010-12-21 Method and apparatus for an action directed to a portion of an electronic structure FI20106357A0 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FI20106357A FI20106357A0 (en) 2010-12-21 2010-12-21 Method and apparatus for an action directed to a portion of an electronic structure
PCT/FI2011/051138 WO2012085347A1 (en) 2010-12-21 2011-12-20 Method and apparatus for performing an operation aimed at a part of an electronic structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FI20106357A FI20106357A0 (en) 2010-12-21 2010-12-21 Method and apparatus for an action directed to a portion of an electronic structure

Publications (1)

Publication Number Publication Date
FI20106357A0 true FI20106357A0 (en) 2010-12-21

Family

ID=43415046

Family Applications (1)

Application Number Title Priority Date Filing Date
FI20106357A FI20106357A0 (en) 2010-12-21 2010-12-21 Method and apparatus for an action directed to a portion of an electronic structure

Country Status (2)

Country Link
FI (1) FI20106357A0 (en)
WO (1) WO2012085347A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111229990B (en) * 2020-01-19 2021-08-17 中义(杭州)医药科技有限公司 Electronic chip tray filler

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4342090A (en) * 1980-06-27 1982-07-27 International Business Machines Corp. Batch chip placement system
JP5017147B2 (en) * 2008-03-06 2012-09-05 東京エレクトロン株式会社 Substrate processing method, program, computer storage medium, and substrate processing system
US20100154870A1 (en) * 2008-06-20 2010-06-24 Nicholas Bateman Use of Pattern Recognition to Align Patterns in a Downstream Process

Also Published As

Publication number Publication date
WO2012085347A1 (en) 2012-06-28

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Legal Events

Date Code Title Description
FD Application lapsed