FI20001644A0 - Procedure for treating an inhibitor key as well as a device - Google Patents

Procedure for treating an inhibitor key as well as a device

Info

Publication number
FI20001644A0
FI20001644A0 FI20001644A FI20001644A FI20001644A0 FI 20001644 A0 FI20001644 A0 FI 20001644A0 FI 20001644 A FI20001644 A FI 20001644A FI 20001644 A FI20001644 A FI 20001644A FI 20001644 A0 FI20001644 A0 FI 20001644A0
Authority
FI
Finland
Prior art keywords
treating
procedure
well
inhibitor
key
Prior art date
Application number
FI20001644A
Other languages
Finnish (fi)
Swedish (sv)
Other versions
FI112013B (en
FI20001644A (en
Inventor
Lauri Paatero
Original Assignee
Setec Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Setec Oy filed Critical Setec Oy
Priority to FI20001644A priority Critical patent/FI112013B/en
Publication of FI20001644A0 publication Critical patent/FI20001644A0/en
Priority to AU2001279831A priority patent/AU2001279831A1/en
Priority to PCT/FI2001/000653 priority patent/WO2002009347A1/en
Publication of FI20001644A publication Critical patent/FI20001644A/en
Application granted granted Critical
Publication of FI112013B publication Critical patent/FI112013B/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/002—Countermeasures against attacks on cryptographic mechanisms
    • H04L9/003—Countermeasures against attacks on cryptographic mechanisms for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
    • G06F2207/7219—Countermeasures against side channel or fault attacks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Storage Device Security (AREA)
FI20001644A 2000-07-11 2000-07-11 Procedure for processing a secret key and device FI112013B (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FI20001644A FI112013B (en) 2000-07-11 2000-07-11 Procedure for processing a secret key and device
AU2001279831A AU2001279831A1 (en) 2000-07-11 2001-07-09 Method of processing a secret key and a device
PCT/FI2001/000653 WO2002009347A1 (en) 2000-07-11 2001-07-09 Method of processing a secret key and a device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FI20001644A FI112013B (en) 2000-07-11 2000-07-11 Procedure for processing a secret key and device

Publications (3)

Publication Number Publication Date
FI20001644A0 true FI20001644A0 (en) 2000-07-11
FI20001644A FI20001644A (en) 2002-01-12
FI112013B FI112013B (en) 2003-10-15

Family

ID=8558762

Family Applications (1)

Application Number Title Priority Date Filing Date
FI20001644A FI112013B (en) 2000-07-11 2000-07-11 Procedure for processing a secret key and device

Country Status (3)

Country Link
AU (1) AU2001279831A1 (en)
FI (1) FI112013B (en)
WO (1) WO2002009347A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10360998B4 (en) 2003-12-23 2008-09-04 Infineon Technologies Ag Protection of chips against attacks

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1020778A (en) * 1996-07-08 1998-01-23 Harumi Takeda Encoding device, decoding device and ic card
AU2557399A (en) * 1998-01-02 1999-07-26 Cryptography Research, Inc. Leak-resistant cryptographic method and apparatus
FI115259B (en) * 1999-07-16 2005-03-31 Setec Oy Procedure for generating a response

Also Published As

Publication number Publication date
AU2001279831A1 (en) 2002-02-05
WO2002009347A1 (en) 2002-01-31
FI112013B (en) 2003-10-15
FI20001644A (en) 2002-01-12

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Legal Events

Date Code Title Description
PC Transfer of assignment of patent

Owner name: GEMALTO OY

MA Patent expired