ES359973A1 - Data Processing System. - Google Patents

Data Processing System.

Info

Publication number
ES359973A1
ES359973A1 ES359973A ES359973A ES359973A1 ES 359973 A1 ES359973 A1 ES 359973A1 ES 359973 A ES359973 A ES 359973A ES 359973 A ES359973 A ES 359973A ES 359973 A1 ES359973 A1 ES 359973A1
Authority
ES
Spain
Prior art keywords
processor
task
register
processors
exchange
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES359973A
Other languages
Spanish (es)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Spain SA
Original Assignee
Alcatel Espana SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Espana SA filed Critical Alcatel Espana SA
Publication of ES359973A1 publication Critical patent/ES359973A1/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q3/00Selecting arrangements
    • H04Q3/42Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54541Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
    • H04Q3/5455Multi-processor, parallelism, distributed systems
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)
  • Exchange Systems With Centralized Control (AREA)

Abstract

In an exchange system one of a number of processors working in parallel is nominated in cyclic order for each processing cycle to take on all new exchange tasks initiated in a cycle, further processing required for any task being continued in later cycles by the processor that took up the task initially. As shown in Fig. 1, an exchange GE sends data to two processors R1, R2 by way of register E and receives processed data by way of register S. The processors Ri, R2 have logic sections RW1, RW2, input buffers ER, output buffers AR, and individual or common storage facilities Sp. The processors are nominated to handle task initiation in alternate processing cycles. At the beginning of each processing cycle instructions from one processor are read out to register S while the other processor takes the task data from register E. In an immediately subsequent time slot of the cycle the one processor takes the exchange task data from E while the other processor is read out to S. Each processor sorts through the task data from E to find its own work and, if so nominated, to take on new work.
ES359973A 1967-11-07 1968-11-07 Data Processing System. Expired ES359973A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE1967ST027547 DE1278766B (en) 1967-11-07 1967-11-07 Method for controlling the exchange of information between two or more computers and computer-controlled devices, for example telecommunication systems, in particular telephone switching systems

Publications (1)

Publication Number Publication Date
ES359973A1 true ES359973A1 (en) 1970-06-16

Family

ID=7461466

Family Applications (1)

Application Number Title Priority Date Filing Date
ES359973A Expired ES359973A1 (en) 1967-11-07 1968-11-07 Data Processing System.

Country Status (4)

Country Link
DE (1) DE1278766B (en)
ES (1) ES359973A1 (en)
FR (1) FR1591319A (en)
GB (1) GB1190498A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RO63302A (en) * 1971-02-23 1978-08-15 Int Standard Electric Corp DEVICE FOR CONTINUOUS CONTROL OPERATION AND INFORMATION PROCESSING AND TRANSMISSION OF DATA TELEGRAMS, TO RAILWAY INSTALLATIONS CONTROLLED PAL COMPUTERS

Also Published As

Publication number Publication date
DE1278766B (en) 1968-09-26
GB1190498A (en) 1970-05-06
FR1591319A (en) 1970-04-27

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