ES2787002T3 - Procedimiento y aparato para compresión de etiquetas de memoria caché - Google Patents

Procedimiento y aparato para compresión de etiquetas de memoria caché Download PDF

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Publication number
ES2787002T3
ES2787002T3 ES16717073T ES16717073T ES2787002T3 ES 2787002 T3 ES2787002 T3 ES 2787002T3 ES 16717073 T ES16717073 T ES 16717073T ES 16717073 T ES16717073 T ES 16717073T ES 2787002 T3 ES2787002 T3 ES 2787002T3
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ES
Spain
Prior art keywords
label
entry
cache
memory
compression
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
ES16717073T
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English (en)
Spanish (es)
Inventor
Pellerin, Iii
Thomas Philip Speier
Thomas Andrew Sartorius
Michael William Morrow
James Norris Dieffenderfer
Kenneth Alan Dockser
Michael Scott Mcilvaine
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Qualcomm Inc
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Qualcomm Inc
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Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
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Publication of ES2787002T3 publication Critical patent/ES2787002T3/es
Active legal-status Critical Current
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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/128—Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/40—Specific encoding of data in memory or cache
    • G06F2212/401—Compressed data
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6032—Way prediction in set-associative cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/62—Details of cache specific to multiprocessor cache arrangements
    • G06F2212/621—Coherency control relating to peripheral accessing, e.g. from DMA or I/O device

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
ES16717073T 2015-05-20 2016-04-08 Procedimiento y aparato para compresión de etiquetas de memoria caché Active ES2787002T3 (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/716,947 US9514061B1 (en) 2015-05-20 2015-05-20 Method and apparatus for cache tag compression
PCT/US2016/026664 WO2016186747A1 (en) 2015-05-20 2016-04-08 Method and apparatus for cache tag compression

Publications (1)

Publication Number Publication Date
ES2787002T3 true ES2787002T3 (es) 2020-10-14

Family

ID=55755783

Family Applications (1)

Application Number Title Priority Date Filing Date
ES16717073T Active ES2787002T3 (es) 2015-05-20 2016-04-08 Procedimiento y aparato para compresión de etiquetas de memoria caché

Country Status (10)

Country Link
US (1) US9514061B1 (OSRAM)
EP (1) EP3298493B1 (OSRAM)
JP (1) JP6724043B2 (OSRAM)
KR (1) KR102138697B1 (OSRAM)
CN (1) CN107735773B (OSRAM)
AU (1) AU2016265131B2 (OSRAM)
ES (1) ES2787002T3 (OSRAM)
HU (1) HUE049200T2 (OSRAM)
TW (1) TWI698745B (OSRAM)
WO (1) WO2016186747A1 (OSRAM)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9996471B2 (en) * 2016-06-28 2018-06-12 Arm Limited Cache with compressed data and tag
US10387305B2 (en) * 2016-12-23 2019-08-20 Intel Corporation Techniques for compression memory coloring
US10061698B2 (en) * 2017-01-31 2018-08-28 Qualcomm Incorporated Reducing or avoiding buffering of evicted cache data from an uncompressed cache memory in a compression memory system when stalled write operations occur
US10254961B2 (en) 2017-02-21 2019-04-09 International Business Machines Corporation Dynamic load based memory tag management
US10229061B2 (en) 2017-07-14 2019-03-12 International Business Machines Corporation Method and arrangement for saving cache power
GB2566469B (en) * 2017-09-13 2021-03-24 Advanced Risc Mach Ltd Cache line statuses
US10831669B2 (en) 2018-12-03 2020-11-10 International Business Machines Corporation Systems, methods and computer program products using multi-tag storage for efficient data compression in caches
US11720495B2 (en) 2019-05-24 2023-08-08 Texas Instmments Incorporated Multi-level cache security
US10983915B2 (en) * 2019-08-19 2021-04-20 Advanced Micro Devices, Inc. Flexible dictionary sharing for compressed caches
US11436144B2 (en) * 2020-04-10 2022-09-06 Micron Technology, Inc. Cache memory addressing
CN114201265B (zh) * 2021-12-10 2025-09-02 北京奕斯伟计算技术股份有限公司 支持物理地址大于虚拟地址的虚拟内存管理方法及装置
KR102781288B1 (ko) * 2022-05-11 2025-03-14 서울시립대학교 산학협력단 명령어를 처리하는 방법 및 이를 위한 프로세서 모듈
KR20250064407A (ko) 2023-11-02 2025-05-09 대한민국(방위사업청장) 안보심리지수 생성방법 및 그 시스템

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9226660D0 (en) * 1992-12-22 1993-02-17 Assersohn Roy J B Database system
JPH086857A (ja) * 1994-06-17 1996-01-12 Mitsubishi Electric Corp キャッシュメモリ
US6122709A (en) * 1997-12-19 2000-09-19 Sun Microsystems, Inc. Cache with reduced tag information storage
US6795897B2 (en) 2002-05-15 2004-09-21 International Business Machines Corporation Selective memory controller access path for directory caching
US7162669B2 (en) 2003-06-10 2007-01-09 Hewlett-Packard Development Company, L.P. Apparatus and method for compressing redundancy information for embedded memories, including cache memories, of integrated circuits
US7512750B2 (en) 2003-12-31 2009-03-31 Intel Corporation Processor and memory controller capable of use in computing system that employs compressed cache lines' worth of information
US7277988B2 (en) * 2004-10-29 2007-10-02 International Business Machines Corporation System, method and storage medium for providing data caching and data compression in a memory subsystem
US8806101B2 (en) * 2008-12-30 2014-08-12 Intel Corporation Metaphysical address space for holding lossy metadata in hardware
US8627041B2 (en) 2009-10-09 2014-01-07 Nvidia Corporation Efficient line and page organization for compression status bit caching
WO2011049051A1 (ja) * 2009-10-20 2011-04-28 国立大学法人電気通信大学 キャッシュメモリおよびその制御方法
JP2012003314A (ja) * 2010-06-14 2012-01-05 Renesas Electronics Corp キャッシュメモリ装置
US8838897B2 (en) * 2011-06-29 2014-09-16 New Jersey Institute Of Technology Replicating tag entries for reliability enhancement in cache tag arrays
US9112537B2 (en) * 2011-12-22 2015-08-18 Intel Corporation Content-aware caches for reliability
US9348762B2 (en) * 2012-12-19 2016-05-24 Nvidia Corporation Technique for accessing content-addressable memory
US9396122B2 (en) * 2013-04-19 2016-07-19 Apple Inc. Cache allocation scheme optimized for browsing applications
US9183155B2 (en) * 2013-09-26 2015-11-10 Andes Technology Corporation Microprocessor and method for using an instruction loop cache thereof
TWI514145B (zh) * 2013-10-21 2015-12-21 Univ Nat Sun Yat Sen 可儲存除錯資料的處理器、其快取及控制方法

Also Published As

Publication number Publication date
AU2016265131A1 (en) 2017-11-02
JP6724043B2 (ja) 2020-07-15
AU2016265131B2 (en) 2020-09-10
TW201706853A (zh) 2017-02-16
TWI698745B (zh) 2020-07-11
EP3298493A1 (en) 2018-03-28
US9514061B1 (en) 2016-12-06
KR20180008507A (ko) 2018-01-24
BR112017024623A2 (pt) 2018-07-31
EP3298493B1 (en) 2020-02-12
CN107735773B (zh) 2021-02-05
CN107735773A (zh) 2018-02-23
JP2018519570A (ja) 2018-07-19
US20160342530A1 (en) 2016-11-24
KR102138697B1 (ko) 2020-07-28
WO2016186747A1 (en) 2016-11-24
HUE049200T2 (hu) 2020-09-28

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