ES2673669B2 - Procedure and circuit for receiving data packets according to the IEEE 802.15.4 standard (MSK) - Google Patents

Abstract

Procedure and circuit for the reception of data packets according to the IEEE 802.15.4 standard (MSK). # The present invention consists of a method and its implementation in the form of a circuit for the reception of data packets constructed according to the IEEE 802.15 standard. 4 and in particular the packages that employ OQPSK modulation with a shaping pulse whose shape is half sine cycle (MSK) in the band of 2.45 GHz. More specifically, the present invention describes the synchronization of these packets where the concept of synchronization comprises the Chip synchronization, symbol synchronization and frame synchronization. The procedure is based on the use of a digital filter that processes the phase differences obtained from a phase receiver. This filter provides two outputs from which the chip and symbol synchronism is detected simultaneously.

Description

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D E S C R I P C I O N

Procedure and circuit for receiving data packets according to

IEEE 802.15.4 standard (MSK)

TECHNICAL SECTOR

The present invention is related, in general, to radio frequency data transmission systems. In particular, the invention relates to the reception of data packets that comply with the IEEE 802.15.4 standard, in particular packages that employ OQPSK modulation with a shaping pulse whose shape is half a sine cycle (MSK) in the 2.45 band. GHz, and specifically to the synchronization of these packets.

BACKGROUND OF THE INVENTION

Certain communication systems use frequency modulations for various reasons, including the potential simplicity in both transmission and reception. On the other hand, certain communication systems use displaced phase quaternary modulations (OQPSK) with a shaping pulse whose shape is half a sine cycle, which can be interpreted as a particular form of frequency modulation (Minimum Shift Keying or MSK) with a Data codification determined, the IEEE 802.15.4 [1] standard being a notable example.

The MSK modulation has a frequency deviation equal to half the chip frequency, the chip being the basic transmission unit. One way to detect these types of signals is to observe the instantaneous phase at a frequency equal to the chip frequency, that is, once per chip. In particular, if this signal is sampled at the end of each chip and the phase difference is made with respect to the previous phase, differences of 90 ° and -90 ° are obtained depending on whether a 1 or a 0 has been transmitted.

A receiver capable of detecting MSK signals in this way is the MSK superregenerative receiver presented to [ES 2 554 992 B2].

The digital communications can be classified in packet mode, the one used in this invention, or in continuous mode or "streaming" and, therefore, each one will have a

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different way to synchronize. In package mode, each package is preceded by a “training” sequence (which we will call a preamble) to achieve synchronization. In some cases, synchronization is maintained until the end of the package thanks to the stability of the oscillator crystals.

In the literature there are different methods of synchronism. Basic material can be found in [2] and [3] while more recent results can be seen in [4] and in their references. These publications present techniques that sample the basic unit of information, chip, of the MSK signal at different frequencies. For example, in [5] the chip sampling frequency is 8 times larger than that of the chip itself, in [6] a perfect method for digital implementation is described and it uses a frequency twice as large as the chip frequency . Another case for example is that of [7]. On the other hand, there are techniques to synchronize with the carrier that operate at the chip frequency but do not achieve the high level synchronization (chip, symbol and frame) required in the IEEE 802.15.4 standard.

[1] IEEE Std 802.15.4-2011 (Revision of IEEE Std 802.15.4-2006), pp. 1-314, 2011.

[2] H. Meyr and G. Ascheid, Synchronization in Digital Communications, ser. Wiley Series in Telecommunications. Wiley, 1990.

[3] F. Xiong, Digital Modulation Techniques, ser. Artech House telecommunications library. Artech House, 2006.

[4] E. Hosseini, "Synchronization techniques for burst-mode continuous phase modulation," Ph.D. dissertation, University of Kansas, Feb 2013. [Online]. Available:
https://oatd.org/oatd/record?record=handle%3A1808%2F12963

[5] D. A. Gudovskiy, L. Chu, and S. Lee, "A novel nondata-aided synchronization algorithm for MSK-type-modulated signals," IEEE Communications Letters, vol. 19, no. 9, pp. 1552-1555, Sep 2015.

[6] A. N. D’Andrea, U. Mengali, and R. Reggiannini, “A digital approach to clock recovery in generalized minimum shift keying,” IEEE Transactions on Vehicular Technology, vol. 39, no. 3, pp. 227-234, Aug 1990.

[7] A. A. D’Amico, A. N. D’Andrea, and U. Mengali, “Feedforward joint phase and timing estimation with OQPSK modulation,” IEEE Transactions on Vehicular Technology, vol. 48, no. 3, pp. 824-832, May 1999.

[EN 2 554 992 B2] Patent: Procedure and circuit for demodulation of frequency modulated signals. Shovel and others, 06/23/2014.

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EXPLANATION OF THE INVENTION

The present invention consists of a procedure and its realization in the form of a circuit for the reception, and in particular the synchronization, of data packets that comply with the IEEE 802.15.4 standard (in particular the packages that employ MSK modulation in the band of 2.45 GHz) The standard defines that for this frequency band the transmitted symbols are transformed into 32 chips each. Therefore, the chips are the basic unit of transmission with duration Tx seconds and these chips are modulated with MSK and transmitted. This type of signal can be detected by calculating the phase difference obtained as the difference between the instantaneous phase of a chip and the instantaneous phase of the chip that precedes it. These phase differences range from -90 ° to 90 ° (through 0 °) depending on the sampling time. If the phase is sampled at the end of each chip, only phases of -90 ° and 90 ° will be obtained depending on whether a 0 or a 1 has been transmitted.

The standard defines that the preamble is formed by eight zero symbols. The zero symbol corresponds to the following chip sequence: 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0. To synchronize with a frame of This standard is available eight times this sequence of chips and then, there are two symbols (expressed in first hexadecimal 7 and then A, from now 7A) that indicate the frame start delimiter (SFD).

When talking about synchronization with this standard, it must be taken into account that there are several levels of synchronization. In this case, as mentioned, it is convenient to sample the signal at the end of each chip (to see only phase differences of -90 ° and 90 °) and therefore, an objective during the preamble is to find the end of each chip. This is called chip synchronization. On the other hand, to be able to decode the symbols properly we will have to find the beginning of the symbols and so! group the corresponding 32 chips. This procedure is called symbol synchronization. Finally, once the receiver is synchronized in these two levels, the frame synchronization that is simply waiting for the consecutive 7A symbols corresponding to the SFD is missing. From this moment the useful data of the package is extracted from the symbols that form the rest of the package. This synchronization method uses an instant phase detector, which samples the phase of each chip once. From these phases, the phase difference between consecutive chips is calculated, so that their value is mapped in the range of -180 ° to 180 °. These phase differences constitute the input of a filter with two coefficient vectors, the (q) and the (i).

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The vector (q) is used to obtain information on the symbol synchronization and the vector (i) for the chip synchronization. Both the filter coefficient vectors and the phase difference vector received have a length of N, multiple of 32.

With the output of the filter (Q) the moment of synchronization of the symbol is decided since a maximum is obtained when the symbols of the preamble "fit" with the vector (q), independently of the chip offset. To decide this moment of synchronization, for each new phase difference received, the value of the filter output (Q) is compared to a threshold Once the threshold is exceeded, the synchronization of the symbol is finished In this position, K, the value of the output is taken of the filter of (I) and the offset value, delta, with respect to the end of the chip is calculated.

From the previous operations, the chip and symbol synchronization is performed. The chips are decoded by assigning positive 1 and negative 0. 0. From this chip decoding, and grouping them into groups of 32 from position K, the received symbols are decoded and the arrival of the chip is expected. SFD frame start delimiter. Upon receipt, the synchronization process is completed. If the SFD wait exceeds the duration of the preamble, the synchronization process is restarted.

The present invention consists of the following essential parts schematized in Figure 1: a system (1) with an input signal (3), from which samples of its instantaneous phase (2) are taken, sampled once per chip by means of the phase detector (4) in an instant that can be modified by the control signals (12) and (13). From phase (2), the phase difference (5) between two consecutive phases (the current minus the previous one) is calculated using a phase differential decoder (6). This phase difference (5) enters the main block of the synchronizer, the filter (7), where the outputs (Q) (8) and (I) (9) are calculated in parallel from the coefficient vectors (q ) e (i) (shown in detail in Figure 2). With the result of the output (Q) (8) it is decided whether there is a synchronization of the symbol by comparing it, by means of the comparator (10), with a threshold (11). The result of the comparison is the control signal (12), whose activation indicates that the symbol synchronization has been achieved. Once this threshold has been exceeded, at time K, the control signal (12) allows, from the output of the filter (I) (9), to calculate the displacement, delta (13), between the current sampling time K and the desired chip synchronization using the equation implemented in block (14):

image 1

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where Tx is the chip period, (I) K is the filter output (I) at the moment K and Imax is the maximum value of the output (I) when reception occurs in an ideal situation (with chip synchronism and absence of noise). In case the threshold (11) is also considered, the block (14) implements the equation with correction:

where a (which can take values between 0 and 1) is the correction factor on the maximum Imax value of the filter output (I).

The delta offset (13), together with the control signal (12) allows the synchronization of the chip, delaying the sampling time of the phase detector (4) a delta time.

On the other hand, from the phase difference (5) the value of the received chip (15) is determined by the chip decoder (16), which assigns value '1' if the phase difference is positive and '0 'If it is negative. The chips (15) constitute the input of the symbol decoder (17), which uses the control signal (12) to correctly group the blocks of 32 chips that constitute the received symbols (18). The symbols (18) constitute the input of the SFD frame start detector (19), which when it detects this frame start (formed by the symbols 7A) activates the control signal (20) that allows the symbols (18) after the start of the frame they are received by the data receiver block (21). Note that the activation of (20) supposes the completion of synchronization at all levels: chip, symbol and frame.

The detail of the filter (7) is shown in Figure 2. The phase differences (5) are entered in a shift register (23) of length N, multiple of 32. To obtain the output of the filter (Q) (8), the results of multiplying each of the phases of this shift register by a coefficient. The grouping of these coefficients into a vector constitutes the vector of coefficients (q) (25). To obtain the filter output (I) (9), the results of multiplying each phase of this shift register by a coefficient are added together. The grouping of these coefficients into a vector constitutes the vector of coefficients (i) (24). The coefficients of the vectors (q) and (i) depend on the preamble with which we want to synchronize, and take a value of 0, ‘c’ or ‘-c’, being usual c = 1. The value of ‘c’ determines the threshold (11), which being variable is bounded by the maximum value that the output (Q) can take under ideal conditions (chip synchronism and no noise).

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BRIEF DESCRIPTION OF THE DRAWINGS

To complement the description that is being made and in order to help a better understanding of the characteristics of the invention, it is accompanied as an integral part of said description, a set of drawings in which with an illustrative and non-limiting character, what has been represented next:

Figure 1.- Shows a block diagram of the system that performs the procedure object of the present invention.

Figure 2.- Shows in detail the filter (5) with two outputs (Q) and (I) consisting of phase samples that are multiplied by the coefficient vectors (q) and (i).

Figure 3.- Shows the details of the preferred realization.

PREFERRED EMBODIMENT OF THE INVENTION

The preferred embodiment is described in Figure 3. The system is formed by a phase receiver, for example, the [ES 2 554 992 B2] super-regenerative receiver (26) that already provides a phase difference (5) of the signal MSK (3) sampled. Note that the receiver (26) includes the phase detector (4) and the differential decoder (6) of Figure 1. This phase difference (5) is quantified at 360 µM intervals. In this realization the intervals are 18 ° since M = 20. The intervals are coded in an orderly manner starting with -10 (180 °) and ending in 9 (180 ° -18 ° = 162 °), passing through -5 (-90 °) and 5 (90 °). The phase difference (5) constitutes the filter input (7), which stores this input in a shift register of length N, N being a multiple of the number of chips, 32, which form a symbol. The outputs (Q) (8) and (I) (9) of this filter are calculated from the phases of this shift register and the coefficient vectors (q) and (i).

The vectors (q) and (i) are obtained by repeating the following vectors (q0) and (i0) Ns times,

q0 = [0 1 0 0 1 0 -1 0 1 1 0 -1 -1 -1 0 1 0 0 0 0 0 -1 0 0 -1 -1 0 0 0 1 1 0] e

i0 = [1 0 -1 1 0 -1 0 1 0 0 -1 0 0 0 1 0 -1 1 -1 1 -1 0 1 -1 0 0 1 -1 1 0 0 -1] where Ns can take values integers from 1 to 8 and in the preferred embodiment Ns = 7 is chosen (which is equivalent to N = 7x32 = 224). The objective is to achieve the synchronization of the symbol receiving only 7 consecutive zero symbols, so

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that there is sufficient time (a symbol) to execute the chip synchronization before receiving the start of the frame. These two coefficient vectors, (q) e (i) or (q0) e (i0), are orthogonal to each other.

With the result of the output (Q) (8) it is decided whether there is a synchronization of the symbol by comparing it, by means of the comparator (10), with a threshold (11). The result of the comparison is the control signal (12), whose activation indicates that the symbol synchronization has been achieved. Once this threshold has been exceeded, at time K, the control signal (12) allows, from the output of the filter (I) (9), to calculate the displacement, delta (13), between the current sampling time K and the desired chip synchronization using the equation implemented in block (14) incorporating the correction:

where a is the correction factor, which in the preferred embodiment takes the value a = 0.65, Tx is the chip period, (I) K is the output of the filter (I) at the moment K and Imax is the maximum value of the output (I) when reception occurs in an ideal situation (with chip synchronism and no noise), that is, Imax = (18 * 7) * 5 = 126 * 5 = 630.

it acts on the sampling instant of the receiver, indirectly through the generator (27) of the quench signal (28) which controls the sampling instant. By delaying the quench signal for a delta time, the sampling time is located at the end of the chip, achieving chip synchronization.

On the other hand, from the phase difference (5) the value of the received chip (15) is determined by the chip decoder (16), which assigns value '1' if the phase difference is positive and '0 'If it is negative. The chips (15) constitute the input of the symbol decoder (17), which uses the control signal (12) to correctly group the blocks of 32 chips that constitute the received symbols (18). The symbols (18) constitute the input of the SFD frame start detector (19), which when it detects this frame start (formed by the symbols 7A) activates the control signal (20) that allows the symbols (18) after the start of the frame, they are received by the data receiver block (21), which is part of the MAC layer, which is responsible, among other functions, for calculating the end of the frame and activating the reset control signal (22 ) which restarts synchronization. Note that the activation of (20) supposes the completion of synchronization at all levels: chip, symbol and frame.

image3

With the calculated delta value (13) and the symbol synchronization indicator (12),

Claims (12)

5 10 fifteen twenty 25 30 35 1. Procedure for receiving data packets according to the IEEE 802.15.4 standard, in particular packets that use OQPSK modulation with a shaping pulse whose shape is half sine cycle (MSK) in the 2.45 GHz band, and specifically the synchronization procedure of these packets where the concept of synchronization comprises chip synchronization, symbol synchronization and frame synchronization characterized by the fact that, a) a front-end provides a phase sample per chip, b) the phase difference between the phase samples of two consecutive chips is calculated, c) the phase difference is processed by a filter (Q) whose coefficients are represented by a vector (q), d) the phase difference is also processed by a filter (I) whose coefficients are represented by a vector (i), e) the values of the vector (q) are such that the filter output (Q) provides information for the symbol synchronization, regardless of the possible chip desynchronization, f) the values of the coefficients of (i) are such that the output of the filter (I) provides information on the chip synchronization, g) when the output of (Q) exceeds a threshold, the synchronization of the symbol has been achieved, h) at the same time that the synchronization of the symbol has been achieved, from the value of the filter output (I) the correction is calculated, delta, which the front-end must do on the sampling moment to achieve the chip sync, i) once the symbol and chip synchronization has been achieved, the successive symbols received until the reception of the symbols corresponding to the start of the frame (SFD) are discarded, at which time the frame synchronization is achieved, j) after achieving the symbol, chip and frame synchronism, the useful data of the package is extracted from the symbols that form the rest of the package. 2. Procedure according to revindication 1, characterized in that the vectors (q) and (i) are orthogonal to each other. 5 10 fifteen twenty 25 30 35 3. Method according to claim 2, characterized in that the coefficients of the vectors (q) and (i) are obtained by repeating the vectors q0 = [0 1 0 0 1 0 -1 0 1 1 0 -1 -1 -1 0 1 0 0 0 0 0 -1 0 0 -1 -1 0 0 0 1 1 0] and i0 = [1 0 -1 1 0 -1 0 1 0 0 - 1 0 0 0 1 0 -1 1 -1 1 -1 0 1 -1 0 0 1 -1 1 0 0 -1] respectively. 4. Procedure according to claim 1, characterized in that in the calculation of the correction, delta, the threshold is taken into account. 5. Method according to claim 1, characterized in that the phase differences are mapped in the range of -180 ° to 180 °. 6. Method according to claim 1, characterized in that the operations necessary for the synchronization of the symbol and chip are carried out in parallel. 7. Circuit for the reception of data packets according to the IEEE 802.15.4 standard, in particular the packages that use OQPSK modulation with a shaping pulse whose shape is half sine cycle (MSK) in the 2.45 GHz band, and specifically the synchronization circuit of these packets where the concept of synchronization comprises chip synchronization, symbol synchronization and frame synchronization characterized by the fact that, a) a front-end provides a phase sample per chip, b) the phase difference between the phase samples of two consecutive chips is calculated, c) the phase difference is processed by a filter (Q) whose coefficients are represented by a vector (q), d) the phase difference is also processed by a filter (I) whose coefficients are represented by a vector (i), e) the values of the vector (q) are such that the filter output (Q) provides information for the symbol synchronization, regardless of the possible chip desynchronization, f) the values of the coefficients of (i) are such that the output of the filter (I) provides information on the chip synchronization, g) when the output of (Q) exceeds a threshold, the synchronization of the symbol has been achieved, h) at the same time that the synchronization of the symbol has been achieved, from the value of the filter output (I) the correction is calculated, delta, that the front-end must make on the instant of sampling to achieve the chip sync, i) once the synchronization of the symbol and chip has been achieved, the successive received symbols are discarded until the reception of the symbols that 10 fifteen correspond to the start of the frame (SFD), at which time the frame synchronization is achieved, j) after achieving the symbol, chip and frame synchronism, the useful data of the package is extracted from the symbols that form the rest of the package. 8. Circuit according to claim 7, characterized in that the vectors (q) and (i) are orthogonal to each other. 9. Circuit according to claim 8, characterized in that the coefficients of the vectors (q) and (i) are obtained by repeating the vectors q0 = [0 1 0 0 1 0 -1 0 1 1 0 -1 -1 -1 0 1 0 0 0 0 0 -1 0 0 -1 -1 0 0 0 1 1 0] and i0 = [1 0 -1 1 0 -1 0 1 0 0 -1 0 0 0 1 0 -1 1 -1 1 -1 0 1 -1 0 0 1 -1 1 0 0 -1] respectively. 10. Circuit according to claim 7, characterized in that in the calculation of the correction, delta, the threshold is taken into account. 11. Circuit according to claim 7, characterized in that the phase differences are mapped in the range of -180 ° to 180 °. 12. Circuit according to claim 7, characterized in that the operations necessary for the synchronization of the symbol and chip are carried out in parallel.