ES2561935A1 - Systems and methods for high-bit rate iterative turbo decoding, low error rate and low complexity (Machine-translation by Google Translate, not legally binding) - Google Patents

Systems and methods for high-bit rate iterative turbo decoding, low error rate and low complexity (Machine-translation by Google Translate, not legally binding) Download PDF

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Publication number
ES2561935A1
ES2561935A1 ES201400890A ES201400890A ES2561935A1 ES 2561935 A1 ES2561935 A1 ES 2561935A1 ES 201400890 A ES201400890 A ES 201400890A ES 201400890 A ES201400890 A ES 201400890A ES 2561935 A1 ES2561935 A1 ES 2561935A1
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Prior art keywords
systems
methods
turbo decoding
low
error rate
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ES201400890A
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Spanish (es)
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ES2561935B2 (en
Inventor
Francisco Javier MARTÍN VEGA
Francisco BLÁNQUEZ CASADO
Francisco Javier LÓPEZ MARTÍNEZ
Gerardo GÓMEZ PAREDES
José Tomás ENTRAMBASAGUAS MUÑOZ
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Universidad de Malaga
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Universidad de Malaga
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Priority to ES201400890A priority Critical patent/ES2561935B2/en
Priority to PCT/ES2015/000161 priority patent/WO2016071546A1/en
Publication of ES2561935A1 publication Critical patent/ES2561935A1/en
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Publication of ES2561935B2 publication Critical patent/ES2561935B2/en
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H03M13/296—Particular turbo code structure
    • H03M13/2963—Turbo-block codes, i.e. turbo codes based on block codes, e.g. turbo decoding of product codes

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  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)

Abstract

Systems and methods for high-bit rate iterative turbo decoding, low error rate and low complexity. The invention relates to a method for turbo decoding in parallel iterative series of high binary regime, low error rate and low complexity characterized because it comprises the use of road metrics (pms) in the right edge of the sub-blocks as metrics of initialization for the next sub-block of the next iteration; and the use of the path states (ml) of the left edge of the sub-blocks to make the last backward travel (tb) from a reliable state of the previous sova decoder, said interchangeable mls in the same iteration. The invention also relates implementations of said method based on the sova and bisova algorithms, as well as an implementation based on a new algorithm, alsova, which constitutes a modification of sova, as well as systems that implement said methods. (Machine-translation by Google Translate, not legally binding)

Description

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Claims (1)

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ES201400890A 2014-11-06 2014-11-06 Systems and methods for turbo iterative decoding of high binary regime, low error rate and low complexity Active ES2561935B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
ES201400890A ES2561935B2 (en) 2014-11-06 2014-11-06 Systems and methods for turbo iterative decoding of high binary regime, low error rate and low complexity
PCT/ES2015/000161 WO2016071546A1 (en) 2014-11-06 2015-11-06 Systems and methods for iterative turbo decoding with a low error rate and of low complexity

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ES201400890A ES2561935B2 (en) 2014-11-06 2014-11-06 Systems and methods for turbo iterative decoding of high binary regime, low error rate and low complexity

Publications (2)

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ES2561935A1 true ES2561935A1 (en) 2016-03-01
ES2561935B2 ES2561935B2 (en) 2016-08-10

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010044919A1 (en) * 2000-05-05 2001-11-22 Edmonston Brian S. Method and apparatus for improved perormance sliding window decoding
EP1391995A2 (en) * 2002-08-20 2004-02-25 NEC Electronics Corporation MAX-LOG-MAP decoding with windowed processing of forward/backward recursions
EP1398881A1 (en) * 2002-09-05 2004-03-17 STMicroelectronics N.V. Combined turbo-code/convolutional code decoder, in particular for mobile radio systems
CN101373978A (en) * 2007-08-20 2009-02-25 华为技术有限公司 Method and apparatus for decoding Turbo code

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010044919A1 (en) * 2000-05-05 2001-11-22 Edmonston Brian S. Method and apparatus for improved perormance sliding window decoding
EP1391995A2 (en) * 2002-08-20 2004-02-25 NEC Electronics Corporation MAX-LOG-MAP decoding with windowed processing of forward/backward recursions
EP1398881A1 (en) * 2002-09-05 2004-03-17 STMicroelectronics N.V. Combined turbo-code/convolutional code decoder, in particular for mobile radio systems
CN101373978A (en) * 2007-08-20 2009-02-25 华为技术有限公司 Method and apparatus for decoding Turbo code

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
U. Dasgupta et al. ¿Parallel decoding of turbo codes using soft output T-algorithms¿. IEEE VTC 2000. Vol 3. September 2000. [en línea] [recuperado el 25-1-2016] Recuperado de Internet < URL: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=886292 > < DOI: 10.1109/VETECF.2000.886292 > *
Zhiyong He et al. ¿Highly-parallel decoding architectures for convolutional turbo codes¿. IEEE Transactions on very large scale integration (VLSI) systems. Vol 14, nº 10, October 2006 [en línea] [recuperado el 25-1-2016] Recuperado de Internet <URL: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1715351&tag=1 > <DOI: 10.1109/TVLSI.2006.884172 > *

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