ES2528305A1 - Método de análisis y diseño de circuitos - Google Patents

Método de análisis y diseño de circuitos Download PDF

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Publication number
ES2528305A1
ES2528305A1 ES201400937A ES201400937A ES2528305A1 ES 2528305 A1 ES2528305 A1 ES 2528305A1 ES 201400937 A ES201400937 A ES 201400937A ES 201400937 A ES201400937 A ES 201400937A ES 2528305 A1 ES2528305 A1 ES 2528305A1
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ES
Spain
Prior art keywords
analysis
circuit
translation
machine
legally binding
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Granted
Application number
ES201400937A
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English (en)
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ES2528305B2 (es
Inventor
Jesús DE COS PÉREZ
Almudena Suárez Rodríguez
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Universidad de Cantabria
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Universidad de Cantabria
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Priority to ES201400937A priority Critical patent/ES2528305B2/es
Publication of ES2528305A1 publication Critical patent/ES2528305A1/es
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Publication of ES2528305B2 publication Critical patent/ES2528305B2/es
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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Image Processing (AREA)
  • Image Analysis (AREA)

Abstract

Método de análisis y diseño de circuitos. La presente invención propone un método para el análisis y posterior diseño de circuitos, que permite obtener las curvas de solución del circuito y los puntos de bifurcación y otros puntos de interés de los circuitos de manera simple, rápida y fiable. El método se basa en los datos obtenidos con una simulación inicial de balance armónico, utilizando un generador de excitación, distinto del generador de entrada, que actúa como fuente de excitación del circuito. Un doble barrido en amplitud y frecuencia de este generador proporciona una función tipo admitancia o impedancia de estas dos variables (amplitud y frecuencia), que permite obtener todos los puntos de interés del circuito y todas las curvas de solución periódicas.

Description

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Claims (1)

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ES201400937A 2014-11-17 2014-11-17 Método de análisis y diseño de circuitos Active ES2528305B2 (es)

Priority Applications (1)

Application Number Priority Date Filing Date Title
ES201400937A ES2528305B2 (es) 2014-11-17 2014-11-17 Método de análisis y diseño de circuitos

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ES201400937A ES2528305B2 (es) 2014-11-17 2014-11-17 Método de análisis y diseño de circuitos

Publications (2)

Publication Number Publication Date
ES2528305A1 true ES2528305A1 (es) 2015-02-06
ES2528305B2 ES2528305B2 (es) 2015-05-26

Family

ID=52440046

Family Applications (1)

Application Number Title Priority Date Filing Date
ES201400937A Active ES2528305B2 (es) 2014-11-17 2014-11-17 Método de análisis y diseño de circuitos

Country Status (1)

Country Link
ES (1) ES2528305B2 (es)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140324398A1 (en) * 2013-04-30 2014-10-30 Freescale Semiconductor, Inc. Method and apparatus for accelerating sparse matrix operations in full accuracy circuit simulation

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140324398A1 (en) * 2013-04-30 2014-10-30 Freescale Semiconductor, Inc. Method and apparatus for accelerating sparse matrix operations in full accuracy circuit simulation

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Rizzoli V. et al.. "Harmonic-Balance Algorithms for the Circuit-Level Nonlinear Analysis of UWB Receivers in the Presence of Interfering Signals". IEEE Transactions On Computer Aided Design Of Integrated Circuits And Systems, 20090401 IEEE Service Center, Piscataway, NJ, US 01/04/2009 vol: 28 No: 4 pags: 516 - 527 XP011253731 ISSN 0278-0070 *

Also Published As

Publication number Publication date
ES2528305B2 (es) 2015-05-26

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