ES2527581T3 - Procedimiento de protección de la ejecución de un código informático mediante redundancia dinámica - Google Patents

Procedimiento de protección de la ejecución de un código informático mediante redundancia dinámica Download PDF

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Publication number
ES2527581T3
ES2527581T3 ES11752574.1T ES11752574T ES2527581T3 ES 2527581 T3 ES2527581 T3 ES 2527581T3 ES 11752574 T ES11752574 T ES 11752574T ES 2527581 T3 ES2527581 T3 ES 2527581T3
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Spain
Prior art keywords
redundancy
execution
function
executed
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
ES11752574.1T
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English (en)
Inventor
Karine Villegas
Laurent Gauteron
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales DIS France SA
Original Assignee
Gemalto SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gemalto SA filed Critical Gemalto SA
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Publication of ES2527581T3 publication Critical patent/ES2527581T3/es
Active legal-status Critical Current
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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/52—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • G06F21/755—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation with measures against power attack

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Hardware Redundancy (AREA)
  • Retry When Errors Occur (AREA)

Abstract

Procedimiento de proteccion de la ejecución de un c6digo informatico por un microprocesador, estando dividido dicho codigo en funciones elementales (1, 2, 3, 4, 5, 6), comprendiendo dicha ejecución la utilización de un contador, llamado NC, actualizado (11, 12, 13, 14, 15) despues de la ejecución de cada dicha función elemental, y de al menos dos variables de protección r0 y r1, caracterizado porque comprende al menos las etapas de: inicialización de las variables de protección, identificación de un punto de redundancia, despues de cada incremento de contador NC, por la aplicacion de una función de comparación FC a dicho contador NC y a dicha variable, Desencadenamiento de una etapa de redundancia cuando dicha función de comparación FC devuelve un exito, consistiendo dicha etapa de redundancia en la aplicacion de una función booleanas "SENS" a la citada variable r1, y en un inicio, en función del valor de retorno de dicha función SENS, de una función "redundancia posterior" o de as funciones elementales ya ejecutadas antes de que el punto de redundancia sea ejecutado de nuevo, o de una función "redundancia anterior" o las funciones elementales ejecutadas despues de que el punto de redundancia identificado sea ejecutado de nuevo, reanudación de la ejecución de dichas funciones elementales que queden eventualmente por ejecutar.

Description

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Claims (1)

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ES11752574.1T 2010-10-21 2011-09-09 Procedimiento de protección de la ejecución de un código informático mediante redundancia dinámica Active ES2527581T3 (es)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP10306148 2010-10-21
EP10306148A EP2450816A1 (fr) 2010-10-21 2010-10-21 Procédé de sécurisation de l'exécution d'un code informatique par redondance dynamique
PCT/EP2011/065679 WO2012052228A1 (fr) 2010-10-21 2011-09-09 Procede de securisation de l'execution d'un code informatique par redondance dynamique

Publications (1)

Publication Number Publication Date
ES2527581T3 true ES2527581T3 (es) 2015-01-27

Family

ID=43881027

Family Applications (1)

Application Number Title Priority Date Filing Date
ES11752574.1T Active ES2527581T3 (es) 2010-10-21 2011-09-09 Procedimiento de protección de la ejecución de un código informático mediante redundancia dinámica

Country Status (3)

Country Link
EP (2) EP2450816A1 (es)
ES (1) ES2527581T3 (es)
WO (1) WO2012052228A1 (es)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1271317A1 (en) * 2001-06-29 2003-01-02 Nagracard S.A. System-on-chip with time redundancy operation
US7152193B2 (en) * 2002-08-13 2006-12-19 Lsi Logic Corporation Embedded sequence checking
US20100107245A1 (en) * 2008-10-29 2010-04-29 Microsoft Corporation Tamper-tolerant programs

Also Published As

Publication number Publication date
WO2012052228A1 (fr) 2012-04-26
EP2450816A1 (fr) 2012-05-09
EP2630605A1 (fr) 2013-08-28
EP2630605B1 (fr) 2014-08-06

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