ES2392298B1 - INTEGRATED CIRCUIT FOR DIGITAL TUNING OF TEMPORARY CONTRAST IN IMAGE SENSORS - Google Patents

Abstract

Integrated circuit for digital tuning of time contrast in image sensors comprising at least one digital active pixel having an optical sensor that generates a current I {sub, sens} as a function of lighting power, a tunable high-pass filter per current that generates an effective current I {sub, eff} from the current I {sub, sens} and a phase-locked loop that generates a current I {sub, tune} from a signal of frequency f { sub, tune} generated by external digital control signals, the current I {sub, tune} being the tuning current of the tunable high-pass filter.

Description

INTEGRATED CIRCUIT FOR DIGITAL TUNING OF CONTRAST

TEMPORARY IMAGE SENSORS OBJECT OF THE INVENTION

The present invention, as expressed in the statement of this specification, refers to an integrated circuit for digital tuning of time contrast in image sensors. Introduces a new topology for tuning the internal time contrast of active focal plane pixels based on variable frequency digital signals. Compared to current technology, the invention has the advantage of increasing the robustness of said tuning against possible variations in both the integration technology and the operating temperature of the circuit. Furthermore, the invention also introduces greater flexibility to implement dynamic tuning in real time.

The main field of application of the present invention is in the fields of information and communication technologies.

Thus the present invention describes a specific microelectronic device for digital capture of dynamic images. These images are decomposed into pixels, the individual value of which is obtained from the reading of a monolithic or hybrid optical sensor. The matrix grouping of these sensors constitutes the focal plane of the image to be captured.

BACKGROUND OF THE INVENTION

The

market of the semiconductors this

experiencing

in these days a growing demand of

devices

laptops able of capture images

dynamics in adverse conditions, such as applications such as automotive night navigation, medical diagnostics or strategic equipment. These imaging devices are based on planar matrices

Focal Plane Array (FPA) formed by Active Pixel Sensor (APS), each containing both the optical sensor element, which captures the incident lighting power and converts it to an equivalent current Isens' as well as its circuit individual signal pre-processing. Modern design techniques for APS cells partially include

[as reflected in patents US5461425, US6707410, US7023369] or completely [patent US6741198] the analog-to-digital converter (ADC) within the APS itself, giving rise to digital active pixels (Digital Pixel Sensor, DPS) that provide digital output of their dout lighting directly at their output · Given the physical space restrictions within the active pixel, the ADC architectures currently adopted for DPS cells are predictive, compared to direct alternatives (eg parallel) and algorithmic (eg successive approximations), since they allow simplifying the analog parts of the ADC.

Likewise, and in order to reduce the power consumption per pixel, said ADC is usually implemented by means of time-based conversion techniques, either of the type "time to first event". (time to first spike) [patents US5565915, US6271 785, US6377303, US6525304, US6559788, US6969879, US7071982, US7164114] or of type "event count"; (spike counting) [patent US7095439]. The advantage of the second strategy is low digital switching activity during analog-to-digital conversion, with consequent reduction in electronic noise. Regardless of the ADC technique chosen at the DPS level, it is convenient to try to reduce the redundant information in the Isens current before its analog-digital conversion.

in order to decrease the necessary capacity for the dout reading channel. In this sense, one of the most used techniques to eliminate redundancy in dynamic images is temporal contrast [patent US5576767], which suppresses the low frequency components of image sequences. For the particular case of DPS, said time contrast requires the insertion of a high-pass filter between the signal captured by the Isens optical sensor and the effective signal Ieff that reaches the ADC stage. In practice, the cut-off frequency of the filter marks the border between the redundant components and the useful information of the dynamic image, therefore its tuning is of special importance. In general, such tuning is implemented at the circuit level using a very low value Itune programmable current

(typically lt; lnA). The main disadvantages of this analog tuning mechanism are: dispersion due to the variability of the integration technology, sensitivity to the operating temperature of the circuit, and corruption due to couplings (crosstalk) originating in one or more neighboring DPS cells.

The integrated circuit presented in this invention memory tries to solve these undesired effects in the analog tuning of the time contrast within the

cell

DPS by means, medium of a topology alternative of

attunement

based in signs digital of frequency

variable

(typically <1KHz) This new strategy

it allows to increase the robustness of said tuning against possible variations in both the integration technology and the operating temperature of the circuit, as well as it allows to isolate the tunings of each DPS cell to avoid coupling (crosstalk) between pixels of the focal plane. Furthermore, the invention also introduces greater flexibility for implementing

a variable tuning in real time depending on the

own content and evolution of the images.

DESCRIPTION OF THE INVENTION

For

achieve the objectives and avoid the

drawbacks

indicated previously, the Present

invention

consists in a circuit integrated for the

digital tuning of time contrast in image sensors comprising a digital active pixel (DPS) incorporating, an optical sensor, a high-pass filter for time contrast, an ADC, and a phase hook loop

(Phase-Locked Loop, PLL) for the digital tuning of the high-pass filter. Said PLL is in charge of generating locally within each DPS cell the Itune tuning current necessary for the high-pass filter of temporal contrast according to the ftune frequency of the external digital control signals.

In comparison with the references of the current state of the art already mentioned above, the invention allows increasing the robustness of the tuning of the temporal contrast of each DPS), since at the focal plane level one or more digital clocks with a frequency of ftune frequency are distributed in instead of a weaker integrity analog Itune current. Also, by matching the high-pass filter and its corresponding PLL by design, it is possible to obtain a low sensitivity of the time contrast tuning with respect to variations in both the integration technology and the operating temperature.

In turn, the digital tuning PLL block incorporates a phase and frequency detector (Phase-Frequency Detector, PFD), a load pump (Charge-Pump, CP), a loop capacity, a voltage-current converter (V / I), and a Current-Controlled Oscillator (CCO).

The working principle of the PLL block of

Digital tuning of the time contrast is as follows: the ftune frequency of the digital control signals external to the DPS cell is compared to the local CCO's own internal frequency using the PFD; the resulting in-phase error signal is sent to the CP for

to be

amplified in the capacity in shape of tension of

attunement

Vtune; bliss tension I know turns then to the

stream

Itune using the converter SAW; the

stream

of attunement resulting I know drift toward the

high-pass filter for tuning the time contrast but also towards the BCC. Thanks to the closed-loop operation with negative feedback of the entire PLL block and ensuring adequate time constants, the echo oscillation frequency is hooked to the ftune frequency of the external digital control signals. Therefore, by ensuring a pairing by design of the high-pass filter and the echo, a tuning of the cutoff frequency of the temporal contrast can be obtained as a function of the external frequency ftune itself. Unlike the tuning discussed in the Current State of the Art, in the new scheme of the present invention it is not necessary to distribute within the focal plane the analog tuning current Itune 'since it is generated locally within each DPS cell based on of the ftune frequency of the digital control signals external to the focal plane. Changing from analog to digital domain of time contrast tuning already allows intrinsically increased integrity against crosstalk due to other DPS cells. In addition, the Itune current generated by the scheme of the new invention may be slightly different in each DPS cell if required by each high-pass filter, if not possible by

the inventions of the State of the Art. Therefore, the new digital time contrast tuning system also allows compensation for drifts caused by deviations in integration technology.

or by the simple fluctuation of the operating temperature of the focal plane.

Thus, the integrated circuit for digital tuning of time contrast in image sensors described in the present application comprises at least one digital active pixel where each digital active pixel comprises at least:

i) an optical sensor that generates an Isens current as a function of an incident lighting power captured by the sensor;

ii) a current tunable high-pass filter that generates an effective current Ieff from the input current Isens, the effective current Ieff being the output of the integrated circuit that provides a measure of the temporal contrast of the digital active pixel

additionally comprising a phase-locked loop that generates an Itune current from a ftune frequency signal generated by external digital control signals, the Itune current being the tuning current of the tunable high-pass filter.

In one embodiment of the invention, the phase locked loop of the circuit at least comprises:

iii) a phase and frequency detector that receives as input the ftune frequency signal from the external digital control signals and a fcco frequency signal from a current controlled oscillator and outputs a digital phase error signal;

iv) a charge pump that receives as input the

digital phase error signal and generates a current error signal at the output;

v) a loop capacity that receives the current error signal as input and integrates it as Vtune voltage;

vi) a voltage-current converter that transforms the Vtune voltage received at the input into the output Itune current, the Itune current being the current tuned by the tunable high-pass filter;

vii) the current-controlled oscillator that receives the Itune output current of the converter-current voltage as input and generates the frequency signal fcco as output.

In another embodiment of the invention, the high-pass filter tunable by the Itune current and the oscillator controlled by the same Itune current are made up of the same basic technological structures and operate at the same temperature.

In another embodiment of the invention, the integrated circuit for digital tuning of time contrast comprises an analog / digital converter located at the output of the tunable high-pass filter to generate a dout illumination digital reading value from the effective current Ieff input.

BRIEF DESCRIPTION OF THE FIGURES

Figure 1: Shows a general diagram of the focal plane matrix formed by digital active pixels. The same figure describes the internal structure of the DPS cell as it is currently manufactured.

Figure 2: Shows the new topology for the digital tuning of the time contrast proposed in the invention.

Figure 3: Shows the internal structure of the PLL for

the digital tuning of the high-pass filter.

Figure

4th: Shows a example of realization of the

filter

He passed high tunable for the circuit of

attunement

digital of the contrast temporary proposed in the

invention.

Figure 4b: Shows an example of embodiment of the PLL for the digital tuning circuit of the time contrast proposed in the invention.

Figure 5: Shows the operation of the exemplary embodiment of the new topology for digital tuning of time contrast proposed in the invention and described in Figure 4.

Figure 6: Shows an example of the electrical simulation results of the exemplary embodiment of the new topology for digital tuning of time contrast proposed in the invention.

DESCRIPTION OF SEVERAL EXAMPLES OF CARRYING OUT THE INVENTION

Next, a description of several embodiment examples of the invention are made, by way of illustration and not limitation, with reference to the numbering adopted in the figures.

Figure 1 shows an example of embodiment of a device belonging to the state of the art where the focal plane matrix (101) is formed by active sensor pixels (102), each containing both the optical sensor element (1 O 4), It captures the incident lighting power (1 O 3) and converts it to an equivalent current Isens (105), as well as its individual signal pre-processing circuit. Said device comprises having the analog-digital converter (1 O 8) within the APS itself (102), giving rise to digital active pixels (102) that supply directly to

its output the digital reading of its dout lighting (109). It also includes a high-pass filter (106) between the signal captured by the Isens optical sensor (1 O5) and the effective signal Ieff (107) that reaches the ADC stage (108).

Figure 2 shows an example of embodiment of the present invention for DPS cells (102), in which a possible circuit implementation of the new digital tuning of time contrast using PLL is detailed.

(201), also including the high-pass filter itself (106). This exemplary embodiment is designed and electrically simulated for a CMOS technology of

O. 35pm powered at 3. 3V, although the same invention is valid for a more modern CMOS technology than O.15pm powered at 1.8V.

Said exemplary embodiment of the circuit comprises a digital active pixel incorporating, an optical sensor (104), a high-pass filter (106) for temporal contrast, an ADC (1 O8), and a phase hook loop (PLL) (201) for the digital tuning of the high-pass filter

(106) Said PLL (201) is in charge of generating locally in each DPS cell (102) the Itune tuning current

(11 O) necessary for the high-pass filter (1 O6) of temporal contrast according to the ftune frequency (202) of the external digital control signals.

FIG. 3 shows the exemplary embodiment with a more detailed view of the PLL. Thus, the digital tuning PLL block (201) in turn incorporates a phase and frequency detector (PFD) (302), a charge pump (CP)

(303), a loop capacity (304), a voltage-current (V / I) converter (306), and a current controlled oscillator (CCO) (301).

The operating principle of the example of the embodiment of the invention is as follows: the frequency ftune (202) of the digital signals of

External control to the DPS cell (102) is compared to the local internal echo frequency (301) itself through the PFD (302); the resulting in-phase error signal is sent to the CP (303) to be amplified in the capacity (304) in the form of the tuning voltage Vtune (305); said voltage is converted 1 u ego to the Itune current (11 O) using the V / I converter (306); the resulting tuning current is diverted to the high-pass filter (106) for tuning the time contrast but also to the echo (3O1). Thanks to the closed-loop operation with negative feedback of the entire PLL block (201) and ensuring adequate time constants, the oscillation frequency of the echo (301) is hooked to the ftune frequency (2 02) of the external digital signals of control. Therefore, by ensuring a design pairing of the high-pass filter (106) and the echo (301) ', a tuning of the cutoff frequency of the temporal contrast can be obtained as a function of the external frequency ftune (202) itself.

As shown in Figures 4a and 4b, the high-pass filter block (106), more specifically shown in Figure 4a, for the temporal contrast is implemented in this case by means of a low-pass filter that feeds back the low-frequency components. Ibias (4 O1) to be subtracted from the Isens signal (1 O5) generated by the optical sensor (1 O4) in order to obtain the effective signal Ieff

(107). This effective signal is integrated into Cint (412) to be sent to the analog-digital conversion stage in the form of a Veff voltage (413). The low-pass feedback filter is performed in this case using logarithmic domain design techniques and consists of: the input compressor implemented using the N-type MOS Field Effect Transistor (NMOSFET) M1 (409) responsible for calculating the

logarithmic equivalent stress Vsens (408); the low-pass MOS-C network implemented by means of the NMOSFET M3 (406) and the NMOS Cbias capacity itself (404) that performs the filtering of Vsens (4 O8) in the logarithmic domain to obtain V bias (4 O3); and finally the expander M2 (4 02) that obtains the low frequency components Ibias (401) back in the current domain to be extracted from Isens (105). The current mirrors formed by M5 transistors

(405), M6 (410) and M7 (411) have a double functionality: carry out the symmetric subtraction of Ibias (4 O1) at the output, as well as optionally copy said Ibias (401) to be reused as a bias current in other DPS cell circuits (102). For this example of realization of the high-pass filter, the analog tuning of the time contrast is given by the Itune current level (110) which, by means of the NMOSFET M4 (407), is in charge of modulating the non-linear resistance of the M3 device (406) in order to control the cutoff frequency of the high-pass filter (106) of the time contrast.

Precisely, the tune current level Itune (11 O) is generated locally through the implementation proposed in figure 4b for the PLL block (2 O1) and which is made up: a NOR type logic gate

(416) and another NAND type (417) for the PFD function

(302) with the corresponding digital slow reverse (418) and fast forward (419) phase and frequency signals; the M8 (420) and N-type M9 (421) M-type MOS transistors that implement the CP (303) in charge of charging and discharging the loop MOS capacity (3 O4) and thus control the tuning voltage Vtune (305) ; P-type MOS transistors M10 (422), M11 (423) and M12 (424) that carry out the V / I conversion (306) to generate the Itune tuning current (11 O) of both the step filter-

high (106) for time contrast such as from the current controlled oscillator (301); and finally the current controlled oscillator (301) implemented in this case by the relaxation network M13 (425), M14 (426), M15 (427), Ceeo (431) and the switches (428,429) that generate the frequency of the digital signal ceo (432) through its analog representation Veeo (430).

The basic principle of operation of the embodiment of the invention is illustrated by the schedule in Figure 5. Based on the difference in phase and frequency between the digital signals ceo (432), the internal oscillator (301), and tune2 ( 415), from the external tuning, the digital slow reverse (418) and fast forward (419) controls are generated. Since the relaxation oscillator's zero crossing threshold Vth (501) is fixed as well as the crossing interval defined by tune1 (414), the frequency change of Veeo

(430), and consequently ceo (432), is performed by modulating the Itune current (11 O), which in turn controls the time-contrast high-pass filter (10 6) itself. Consequently, the cutoff frequency fe at -3dB of said high-pass filter (106) of temporal contrast is automatically tuned to fe = (1 / rr) * (Ceeo / Cbias) * ln [(1 + Y) / ( 1 + 1 / X)] * ftune •

Based on the circuit described in Figure 4 and the operating principle of Figure 5, the results of the electrical simulation for the design case

(Ceeo / Cbias) = 15, X = 1 and Y = 2 are presented in Figure 6. The graph demonstrates the linearity of the cutoff frequency fe (601) at -3dB of the high-pass filter.

(106) of temporal contrast of the DPS cell (102) with respect to the frequency ftune (2 02) of the external digital tuning signals. Furthermore, said linearity is maintained over a wide frequency range not only

for the case temperature 60 ° C (603) and (604). This

5 classic of Figure l. typical of the CMOS technology used and for an environment of 27 ° C (602), but also for the slowest case of CMOS technology, robustness is not obtained by means of the current State of the Art solution illustrated in the

Claims (4)

1. Integrated circuit for digital tuning of time contrast in image sensors comprising at least one digital active pixel where each digital active pixel comprises at least: i) an optical sensor that generates an Isens current as a function of an incident lighting power captured by the sensor; ii) a current tunable high-pass filter that generates an effective current Ieff from the input current Isens, the effective current Ieff being the output of the integrated circuit that provides a measure of the temporal contrast of the digital active pixel characterized in that it comprises a phase-locked loop that generates an Itune current from a ftune frequency signal generated by external digital control signals, the Itune current being the tuning current of the tunable high-pass filter.

2.

Circuit integrated for the digital tuning of the

contrast

temporary in sensors of image, according the

vindication

one, characterized why the tie of

hitch

of phase to the less understands:

i) a phase and frequency detector that receives as input the ftune frequency signal from the external digital control signals and a fcco frequency signal from a current controlled oscillator and outputs a digital phase error signal; ii) a charge pump that receives the digital phase error signal as input and generates a current error signal at the output; iii) a loop capacity that receives the current error signal as input and integrates it as Vtune voltage; iv) a voltage-current converter that transforms the Vtune voltage received at the input into the output Itune current, the Itune current being the current tuned by the tunable high-pass filter; and, v) the current-controlled oscillator that receives the Itune output current of the converter-current voltage as input and generates the frequency signal fcco as output.

3.

Integrated circuit for digital tuning of time contrast in image sensors, according to claim 2, characterized in that the high-pass filter tunable by the Itune current and the oscillator controlled by the same Itune current are made up of the same basic technological structures and operate at the same temperature.

Four.

Integrated circuit for digital tuning of time contrast in image sensors, according to claim 1, characterized in that it comprises an analog / digital converter located at the output of the tunable high-pass filter that generates a digital reading value of dout lighting from the effective input current Ieff.