ES2331523T3 - CROSS-COMPARED MEMORY-BASED COMPARISON FOR SYSTEMS SUBJECT TO CROSSED VERIFICATION. - Google Patents

Abstract

A cross compare solution running in a multiprocessor configuration, using a multi-port RAM with built-in logic. This provides for a fast and simple data cross compare medium. The multi-port RAM unit can be plugged into the motherboard of the main processor unit, requiring no external hardware or wiring. A method and a system for cross compare has a first layer of buffers with a first storage area for storing information from the first processor and a second storage area for storing information from the second processor, and a second layer of buffers with a third and fourth storage areas, where each storage area stores information from the first and second storage areas. The first, second, third, and fourth storage areas have one or more buffers allocated only for its respective storage area.

Description

Memory-based cross comparison for systems under cross-checking.

1. Field of the invention

Cross comparison for systems operating in a multiprocessor configuration, such as configurations dual 2 of 2 and triplicate configurations 2 of 3 or some other multiprocessor configuration

2. Description of the related technique

However the speeds of CPU units clock and have become more common the multiprocessor architectures, performance capabilities Processing have exceeded those of traditional RAM. A solution to this problem has been the adoption of a RAM multiport

A multiport RAM comes in many configurations that provide access to a memory space shared through several input and output ports. Every the ability to write several data is more common simultaneously on the device through separate ports, When data is written simultaneously in the same place from two or more ports, the integrity of the data is not guaranteed. The addressed memory location may contain new data, old data or some transitional value. To mitigate this problem additional logic is required to implement a arbitration. Arbitration consists in coordinating places of access to memory by processors.

Some applications of computer systems digital, for example, vital systems and critical systems for a mission, require a high degree of security. For example, for a safe operation, a flight control computer of a aircraft depends on a continuous computing operation exempt from errors during the entire flight period. It should be recognized that an error-free operation requires the elimination of defects or the confinement of these within the computer system digital. In addition to increasing demands for reliability, it is a fast computing system with total performance is necessary increased for flight control systems and other systems vital.

To provide data integrity, more of a processor determines if there is discrepancy in the information which is being transferred simultaneously by a bus. The comparison of data to obtain highly accurate results is called frequently "cross comparison." For example, performing a cross comparison of computational results produced high integrity of different processors is provided the data.

The current cross-comparison systems that operate in a multiprocessor configuration are slow, require a lot of software and are complicated in its installation. There are some currently available solutions. A solution used to Dual systems require a parallel or serial port connection. Both parallel and serial port solutions support only a limited amount of data that can be transferred from one time. The serial port based solution is slow and requires a lot of software The parallel port solution becomes slow whenever large amounts of data need to undergo cross comparison.

Another solution is for systems triplicates that use a complicated hardware installation or a high speed signal connection that requires a lot of software and uses external wiring. When they were implemented using external rack-based hardware, installation was complicated and it required a lot of software. When they were implemented with a High speed serial communication (Ethernet), the layout it required a lot of software and was limited in speed by the external wiring

As an example of a technique system related, U.S. Patent No. 6,182,196 describes a method and apparatus for arbitrating requests for access to a memory. The memory comprises a cross verification module (502) that compares customer operation requests. When the cross-check module (502) determines that the requests are trying to access a block at one time identical memory, cross comparison (502) arbitrates between Customer operation requests. The arbitration is based in an arbitration rule and produces a first request for access to memory and a second request for memory access.

As another example of a previous system, the Publication of US patent application 2002/0010902 describes field programmable door groupings (FPGAs) that they comprise an embedded RAM block (EBR). In one embodiment, the EBRs are multiport RAM blocks embedded in an FPGA core. The EBR It is used to increase the amount of memory and complement the Distributed memory of the programmable functional unit. Be provides arbitration between write ports, and a unit of arbitration receives memory request signals and selects a winner of the requests.

Document DE 198 09 089 A1 describes a method cross-comparison of data between a plurality of channels of processing, where a plurality of plates are used coupling that are connected to each other through a separate bus system to implement a mechanism of replication.

Summary of the invention

The present invention relates to a computer multiprocessor according to claim 1 and to a method according to the claim 9.

The attached claims must Consult to find out the true scope of the invention.

The present invention is a solution of cross comparison that develops in a configuration multiprocessor An aspect of the present invention consists in provide a means of quick and easy cross-comparison of data using a multiport RAM with built-in logic. The Multiport RAM can be plugged into the backplane of the unit multiprocessor that connects to any standard bus or even non-standard. Therefore, no hardware or wiring is required external

The cross comparison system according to the The present invention employs a transitory storage method of data that operates at a fast speed limited only by the memory access time The system is simple to implement. and does not require a communication protocol.

In an exemplary embodiment the system is fits on a single plate and does not require conductive wires external The concept is not linked to any specific hardware and It is valid in terms of architecture and hardware implementation for any cross-comparison data size and any communication speed required. Therefore, if the size and / or speed requirements, the system given as example can be easily improved by replacing the unit.

The cross-comparison solution based on memory according to the present invention is based on a multiport RAM with its required logic, implemented, for example, using a grouping of field programmable doors (FPGA) or a circuit integrated for specific applications (ASIC).

The multiport RAM according to the present invention offers controlled write and read access for each unit system processor, providing a means of comparison Fast and simple data cross. Full separation is provided among all the processing units of the system. Since it is not possible simultaneous access to any place in memory, it is not Arbitration necessary. The system of the invention is ideally suitable for, among other things, security systems, systems critical for a mission or high availability systems that they are all subject to cross-checking and that computer based.

According to an embodiment of the present invention, a cross comparison system is provided for a computer multiprocessor that has at least one first and one second processor. The system includes a first layer of buffers that comprises a first storage area to store information from the first processor and a second storage area to store information from the second processor. Be It also provides a second layer of buffers. The second layer of buffers comprises a third storage area to store the information from the first storage area and the information from the second storage area, and a fourth storage area to store information from of the first storage area and the information coming from the Second storage area. The information coming from the first storage area and the second storage area is automatically transferred to the third storage area and to the Fourth storage area. The first storage areas, second, third and fourth comprise at least one assigned buffer only to their respective storage area.

The first processor reads the information from the third storage area and declare a satisfactory cross comparison if it is determined that the information from the second processor is substantially identical to the information coming from the comparison processor. Also, the second processor reads the information coming from the fourth storage area and declare a cross comparison satisfactory if it is determined that the information from the second processor is substantially identical to the information from the comparison processor.

Another embodiment of the present invention it consists of a method of cross-comparison between places in a multiport memory written simultaneously by several processors, each port being provided with a buffer of a plurality of buffers of the first layer. In the first step of method each processor writes data for comparison crossed in the buffer of the plurality of first layer buffers corresponding to the respective processor port. The data written in all buffers of the first layer are transferred then to a plurality of buffers of the second layer, providing each buffer of the plurality of buffers of the second layer a storage area for each buffer of the plurality of buffers of the first layer, and being provided a buffer of the plurality of buffers of the second layer for each of the various processors

Each processor then reads the information from a respective buffer of the plurality of seconds buffers and compare the information read in your plurality buffer of second buffers, declaring a cross comparison satisfactory if information from another processor is overlap with information from the comparison processor in terms of storage areas that are written by processors The plurality of processors are synchronized before the transfer of data from the first buffer layer to the second layer of buffers.

The second embodiment may further describe determining whether there is additional information that should undergo a cross comparison, and, if so, the repetition of the steps with the additional information, starting at the step of writing for each data processor that must undergo cross comparison.

Brief description of the drawings

The present invention will now be described with detail describing illustrative non-limiting embodiments of the same with reference to the attached drawings. In the drawings the same reference characters denote analogous elements:

Figure 1 illustrates an overview of the solution for a triplicate security system according to a illustrative non-limiting embodiment of the present invention.

Figure 2 illustrates the steps of a method executed in a cycle of an application according to an embodiment Non-limiting illustration of the present invention.

Figure 3 illustrates steps of a method for run a cross comparison according to an illustrative embodiment non-limiting of the present invention.

Detailed description of embodiments not limiting

A cross comparison is usually performed at beginning and before the end of each cycle of an application, what which is described here in more detail below. During this activity, all entrances and / or exits are subjected to a cross comparison between processors, such as units multiprocessors / central processing units (MPUs / CPUs), microprocessors, the vital time control units of execution, etc.

Figure 1 illustrates a configuration 2 of 3 of in accordance with the example of non-limiting embodiment of the present invention. Referring to the system illustrated in Figure 1, each CPU (20, 21, 22) of a security system 10 represents a CPU example or an example of MPU or some other example of processor, depending on the particular application. The terms CPU, MPU and processor are used interchangeably here. The performing cross-comparison is only one of the functionalities of each processor.

Each CPU (20, 21, 22) uses its own bus to connect to a multiport RAM (30). In multiport RAM 30 Each CPU has its own memory space. To CPU1 (20) it assign a write-only buffer 1.1 (40) and a buffer-only reading 1.2 (50); a buffer of only 2 is assigned to CPU2 (21) write 2.1 (41) and a read-only buffer 2.2 (51); and to CPU3 (22) a write-only buffer 3.1 (42) and a buffer of read only 3.2 (52). The terms of only writing and only reading are used here with reference to the capacity of the CPUs of accessing a buffer.

Strict access is provided controlled to the memory space of each CPU. The buffer of read-only for each CPU includes a record for each of the write-only buffers. In the present example each buffer of Read only (50, 51, 52) has three records (1.1, 2.1, 3.1). The data written by each CPU (20, 21, 22) are copied through an internal logic (60, 61, 62) to pass them from all buffers write-only (40, 41, 42) to a corresponding record of each Read-only buffer (50, 51, 52) for each CPU. This means Two layers of buffers are planned. A layer consists of buffers write-only (40, 41, 42) and the second layer consists of buffers read-only (50, 51, 52). The data written in the buffer of write only 1.1 (40) by CPU1 (20) are copied to registers 1.1 of read-only buffers (50, 51, 52). Similarly, the data written in write-only buffer 2.1 (41) by CPU2 (21) and the data written in the write-only buffer 3.1 (42) by CPU3 (22) are copied in registers 2.1 and 3.1, respectively, of read-only buffers (50, 51, 52). In other words, in the illustrative non-limiting embodiment of each processor (20, 21, 22) has one or more buffers of the first layer of buffers (40, 41, 42) and one or more buffers of the second layer of buffers (50, 51, 52).

The internal logic that controls the process of Data transfer is implemented using FPGAs or ASICs (60, 61, 62). As illustrated in Figure 1, for the purpose of synchronization, special logic can be implemented in an FPGA or ASIC (60, 61, 62) in order to ensure that, while a CPUs (20, 21, 22) write in their place of memory, the others can read only "not ready" in your own place. FPGAs or ASICs perform logical operations required for the buffers of the first and second layers. Each processor (20, 21, 22) has its own FPGA itself or individual ASIC (60, 61, 62), respectively.

In addition, it is preferable to provide a source of Individual power (70, 71, 72) for each FPGA or ASIC (60, 61, 62). Making each processor (20, 21, 22) have its own FPGA or individual ASIC (60, 61, 62) powered by its source of Individual feeding (70, 71, 72) ensures a separation between the processors (20, 21, 22). For example, if a processor turns out to be defective, it can be simply isolated and its data will be discarded, without impact on others processors This means that the processors that work they usually disconnect themselves from the defective processor in case of an error detection in the cross comparison. A ordinary subject matter expert will know how to isolate a processor defective, and the various isolation techniques fall within the scope of the invention.

A cross comparison for the system illustrated in figure 1 is done by means of the steps illustrated in figures 2 and 3. First, figure 2 shows the CPU cycle according to this embodiment illustrative In particular, they turn on and initialize (step 201) the processors by any conventional technique known. An ordinary expert in the field would easily know a series of ways to turn on and initialize a processor. After the processors have been initialized, it is implemented  (step 202) a cross comparison of the entries. The comparison cross entry (step 202) according to the example of embodiment is described in more detail in relation to figure 3. After cross-comparing the entries (step 202), performs (step 203) a series of foreground tasks of the application.

For example, each processor can be performing a variety of computing operations very complex. When the foreground tasks of the application, output, for example the result of operations computing, is also subjected to a cross comparison (step 204). The cross comparison of the outputs according to the exemplary embodiment is described in more detail in relation to Figure 3. After the outputs of the operations of computation are cross-checked (step 204) by processors, the application cycle (205) is completed and can start a new cycle (205).

In this exemplary embodiment, each processor it will be reported that the cross comparison has been completed without No signaling to the other processors. After the satisfactory cross comparison the input and / or output will be available for scrutiny. As an alternative, the entrance and / or the outputs can be provided generating an interruption. He scrutiny, interruption generation or some other solution They are within the scope of the invention. The chosen solution It will depend on the application and the hardware used.

Next, with reference to Figure 3, a detailed description of the example of non-limiting cross comparison of the inputs and / or outputs (203, 205) will be given. Figure 3 shows the synchronization of the CPUs (step 301). Synchronization can be performed by hardware and / or software, using any number of techniques. As an example of one of the many ways in which synchronization can be achieved, the three CPUs can scan a specific memory location, one for each CPU, where the other CPUs will update their readiness for cross-comparison. Reading the memory location deletes the updated value in order to avoid rancid information. Special logic can be implemented in an FPGA or ASIC to ensure that, while one CPU writes instead of memory, the others can only read "not ready" instead
own.

Synchronization can occur in a diversity of sites as long as the processors are synchronized before transferring data to the buffer layer only reading (50, 51, 52). For example, they can be written so asynchronous data in the first buffer layer, the only layer reading (40, 41, 42). Synchronization (301) would take place then before transferring data to the second layer of buffers (50, 51, 52). In addition, in this embodiment example provides a special delay time to prevent cycle overshoots, which is considered a major failure of the processor. For example, if a processor 20 was isolated due to to some failure, processors 21 and 22 will continue with the cross comparison after a predetermined period of time, the special delay time, even if a successful synchronization with processor 20. This prevents a absolute blocking of processors 21 and 22 that work usually.

In the example illustrated in Figure 3 the CPUs are synchronized before writing data to the first layer of buffers In particular, once the CPUs are synchronized, each CPU writes the data to be cross-checked in its respective write-only buffer (step 302). The data from each write-only buffer are transferred then to each read-only buffer (step 303) using a logic implemented in the FPGA or ASIC (60, 61, 62).

Each CPU then reads the data for all three CPUs (20, 21, 22) in their respective read-only buffer (50, 51, 52) (step 304) and compare your data with the data from the other processors (step 305). A cross comparison will be declared satisfactory if at least 2 of 3 data submitted for comparison crossed in a read-only buffer are identical (step 306). By example, processor 20 will compare data stored in the record 1.1 with data contained in records 2.1 and 3.1 located in buffer 50. It is a cross comparison satisfactory when the information from record 1.1 of the buffer 50 overlaps with information from records 2.1 and / or 3.1 of buffer 50.

A satisfactory cross comparison can be declared by any of the CPUs, each of which does Your own comparison of the data. If a CPU determines that there is identical data from two other CPUs, but their own data is not identical to data from any of the other CPUs, a satisfactory cross comparison is not declared by part of that CPU. However, in this circumstance the two CPUs that gave rise to the identical data will declare each one of them a satisfactory cross comparison (step 306) based on your comparisons of data from their respective buffers Own read only.

For a large amount of data that should undergo cross comparison, that is, exceeding the RAM capacity, after step 304 a determination regarding whether all data have been submitted to cross comparison (step 307). If there is any remaining data, the sequence returns to step 302, writing each processor the following data to be cross-checked in the respective write-only buffer. Only when it is determined that They exchanged all the data will follow step 305.

You can skip step 307 implemented a RAM large enough, since the need for step 307 depends of the size of the data to be compared crusade. In order to have the best response time, an area of large cross comparison will ensure that the comparison process cross can be done with a data packet.

Systems such as vital control units in Real time (RTVCUs) are an example of an ideally system suitable for use with the cross comparison solution previously described. No new protocols are required. communication, and the solution is limited only by the time of memory access

The following characteristics may constitute also advantageous embodiments of the invention:

-

He claimed multiprocessor computer, in which time is expected delay to read data from the buffers of the second layer to perform cross comparison by processors;

-

He claimed multiprocessor computer, in which the processors before cross comparison, and in which it detects synchronization by means of buffer scrutiny of the second layer by each of the processors;

-

He claimed multiprocessor computer, in which each of the processors is a central processing unit, a microprocessor, a vital runtime control unit and a multiprocessor unit;

-

He claimed multiprocessor computer, in which the buffers of the first and second layers form a random access memory multiport plugging into a backplate of the processors that connect to a standard bus or a non-bus standard;

-

He claimed multiprocessor computer, in which some FPGAs or ASICs perform logical operations required for the buffers of the first and second layers, and in which an FPGA or ASIC is planned individual for a storage area of the layer buffers first and second assigned to a particular one of the processors;

-

He claimed multiprocessor computer, in which a individual power supply for each of the FPGAs or ASICs;

-

He claimed multiprocessor computer, wherein said data stored in the logs are an entry to an operation of computing or an exit from the computing operation;

-

He claimed method of performing a cross comparison, in which said synchronization is performed before the orderly step (a) to write simultaneously the information to be compared crossed in said plurality of buffers of the first layer;

-

He claimed method of performing a cross comparison, in which said synchronization is performed after the orderly step (a) to write the information to be submitted asynchronously crossed in said plurality of buffers of the first layer;

-

He claimed method of performing a cross comparison, in which said data synchronization and said cross comparison are performed twice for each processor cycle, once at the beginning of processor cycle for input data and the other at the end of processor cycle for output data;

-

He claimed method of performing a cross comparison, in which said comparison of the output data is made after computational processing in each of the plurality of processors;

-

He claimed method of performing a cross comparison, in which said data transfer in the steps ordered (a) and (b) and said computational processing are performed by a plurality of FPGAs or ASICs, and in which at least one FPGA or ASIC is provided for each of the at least three processors;

-

He claimed method of performing a cross comparison, in which each of the buffers of the second layer comprises at least one separate record for each processor of said at least three processors;

-

He claimed multiprocessor computer, in which the first layer of buffers are write-only buffers and in which the second layer of buffers are read-only buffers;

-

He claimed multiprocessor computer, in which the processors write data asynchronously in the buffers of the first cap;

       \ newpage
    

-

He claimed multiprocessor computer, in which, when the information from the comparison processor does not match the information of the other two processors, the successful cross comparison and the processor is isolated from comparison;

-

He cross comparison system described and / or claimed for a three processor computer, in which each storage area of the second layer of buffers, namely a fourth, a fifth and a sixth storage areas, includes a record, namely a first, a second and a third record, for each processor, to know, the first, the second and the third processor, in which the first processor compares the information stored in the first record of the fourth storage area with the information stored in the second record and with the information stored in the third record of the fourth storage area, in which the second processor compares the information stored in the second registration of the fifth storage area with the information stored in the first record and with the information stored in the third record of the fifth storage area, and in which the third processor compares the information stored in the third registration of the sixth storage area with the information stored in the first record and with the information stored in the second record of the sixth storage area;

-

He claimed multiprocessor computer, which is provided for each one of said processors an individual port to transfer information of their respective storage area of the second layer of buffers to a respective processor to perform said comparison.

The above description of embodiments Non-limiting illustrative has been given by way of example. The above and other features of the invention, including various new method steps and various new components, have been particularly described with reference to the attached drawings and indicated in the claims. It will be understood that the process and the particular construction of parts that materialize the invention is shown by way of illustration only and not of limitation of the invention The principles and characteristics of This invention can be used in many different ways. embodiments without departing from the scope of the invention such as It is defined by the appended claims.

Claims (11)

1. A multiprocessor computer (10) that has at least a first and a second processor (20, 21, 22) and a cross comparison system, said system comprising cross comparison: a first layer of buffers (40, 41, 42) that comprises a first storage area to store information from the first processor (20) and a second area of storage to store information from the second processor (21); a second layer of buffers (50, 51, 52) that it comprises a third storage area to store the information from said first storage area and the information from said second storage area, and a fourth storage area to store information from of said first storage area and the information coming from said second storage area, wherein each of said areas First, second, third and fourth storage is implemented within a multiport RAM (30) and comprises at least one buffer assigned only to its storage area within that RAM multiport (30), said comparison system further comprising crossed an internal logic (60, 61, 62) arranged within said Multiport RAM (30), said internal logic being configured (60, 61, 62) to synchronously transfer the information of said first storage area and said second storage area a said third storage area and to said fourth area of storage, wherein said first processor (20) is configured to read the information of said third storage area and to compare data stored in the third storage area from the first storage area with stored data in the third storage area from the second area of storage to determine if the information stored in said third storage area from the first area of storage is identical to the information stored in the third storage area from the second storage area; Y wherein said second processor (21) is configured to read the information of said fourth storage area and to compare data stored in the fourth storage area from the first storage area with data stored in the fourth area of storage from the second storage area in order of determining whether the information stored in said fourth area of storage from the first storage area is identical to the information stored in the fourth storage area from the second storage area. 2. The multiprocessor computer according to the claim 1, wherein the first layer of buffers (40, 41, 42) they are write-only buffers and in which the second layer of buffers (50, 51, 52) are read-only buffers. 3. The multiprocessor computer according to the claim 2, wherein the first and second processors (20, 21) write data asynchronously in buffers (40, 41, 42) of the first layer and in which the data of the buffers (40, 41, 42) of the first layer are transferred synchronously to the buffers (50, 51, 52) of the second layer. 4. The multiprocessor computer according to claim 1, characterized in that said internal logic (60, 61, 62) comprises FPGAs and / or ASICs. 5. The multiprocessor computer according to claim 1, characterized in that said internal logic (60, 61, 62) comprises its own individual FPGA and / or ASIC for each of said processors (20, 21, 22). The multiprocessor computer according to claim 5, characterized in that each individual FPGA and / or ASIC (60, 61, 62) is powered by an individual power supply (70, 71, 72). 7. The multiprocessor computer (10) according to the claim 1, wherein said multiprocessor computer (10) is configured to isolate said first processor (20) when not match the data that is being compared in said first processor (20), and wherein said multiprocessor computer (10) is configured to isolate said second processor (21) when not match the data that is being compared in said second processor (twenty-one). 8. The multiprocessor computer (10) according to the claim 1, wherein each of said storage areas third and fourth comprises a first record for the data from the second storage area and a second record for data from the second storage area, and each one of said first and second processors (20, 21) is configured to compare data from the first record with data from the second record and to declare a cross comparison satisfactory when the data in the first record is identical to the data in the second record, both records being first and second in a storage area assigned exclusively to a comparison processor 9. A method of cross-comparing for a multiprocessor computer (10) that has at least three processors (20, 21, 22), where each of said at least three processors (20, 21, 22) use a separate memory location from a multiport RAM (30) and where each of said at least three processors (20, 21, 22) is provided with an individual port of said multiport RAM (30) and each of the individual ports it is provided with a respective buffer of a plurality of buffers (40, 41, 42) of a first layer, the method comprising the steps ordered to: (a) have each processor (20, 21, 22) write information to cross-check in the buffer of said plurality of buffers (40, 41, 42) of the first layer corresponding to the port of the respective processor; (b) transfer synchronously written information in all buffers of the plurality of buffers (40, 41, 42) from the first layer to a plurality of buffers (50, 51, 52) of a second layer by means of an internal logic (60, 61, 62) arranged within said RAM multiport (30), providing each buffer with the plurality of buffers (50, 51, 52) of the second layer a storage area for each buffer of the first plurality of buffers, and being provided a respective buffer of the plurality of buffers (50, 51, 52) of the second layer for each of the plurality of processors (20, 21, 22), where the plurality of buffers (40, 41, 42) of the first layer and the plurality of buffers (50, 51, 52) of the second layer are implemented within said multiport RAM (30); (c) do that each processor (20, 21, 22) read the information of a buffer respective of the plurality of buffers (50, 51, 52) of the second cap; and (d) have each processor (20, 21, 22) compare the information read in your buffer of the plurality of buffers (50, 51, 52) of the second layer and declare a cross comparison satisfactory if the information of another processor matches with comparison processor information, where said at least three processors (20, 21, 22) are synchronized before executing the transfer of information in the orderly step (b). 10. A method of making a comparison cross according to claim 9, further comprising a step ordered to: (e) determine if there is additional information to submit to cross comparison, and if so, repeat the steps with the additional information, beginning in step (a). 11. A method of making a comparison cross-section according to claim 9, further comprising detecting a satisfactory synchronization for each of said plurality of processors (20, 21, 22) through a scrutiny of their buffer corresponding to the plurality of second buffers (50, 51, 52), and in which when, after a predetermined period of time, it is not detected by a processor of the plurality of processors (20, 21, 22) successful synchronization between all processors of said plurality of processors (20, 21, 22), execute a time delay operation and perform the Comparison of information by the processor.