ES2325921T3 - POWER SWITCHING CELL, AND CELL MANUFACTURING PROCEDURE. - Google Patents
POWER SWITCHING CELL, AND CELL MANUFACTURING PROCEDURE. Download PDFInfo
- Publication number
- ES2325921T3 ES2325921T3 ES04300311T ES04300311T ES2325921T3 ES 2325921 T3 ES2325921 T3 ES 2325921T3 ES 04300311 T ES04300311 T ES 04300311T ES 04300311 T ES04300311 T ES 04300311T ES 2325921 T3 ES2325921 T3 ES 2325921T3
- Authority
- ES
- Spain
- Prior art keywords
- substrate
- components
- cell according
- sheet
- faces
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 239000012809 cooling fluid Substances 0.000 claims abstract description 10
- 239000003989 dielectric material Substances 0.000 claims description 12
- 238000005304 joining Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 11
- 239000004020 conductor Substances 0.000 abstract description 2
- 239000011449 brick Substances 0.000 description 19
- 229920005989 resin Polymers 0.000 description 7
- 239000011347 resin Substances 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000003466 welding Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 210000001364 upper extremity Anatomy 0.000 description 2
- DQBHVPOZFIIAOT-UHFFFAOYSA-N 1-[2-(2-iodophenyl)ethyl]pyrrole-2,5-dione Chemical compound IC1=CC=CC=C1CCN1C(=O)C=CC1=O DQBHVPOZFIIAOT-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000000110 cooling liquid Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 210000003414 extremity Anatomy 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/112—Mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
- H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/074—Stacked arrangements of non-apertured devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01057—Lanthanum [La]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01058—Cerium [Ce]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Inverter Devices (AREA)
- Rectifiers (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrical Discharge Machining, Electrochemical Machining, And Combined Machining (AREA)
- General Induction Heating (AREA)
Abstract
Description
Célula de conmutación de potencia, y procedimiento de fabricación de la célula.Power switching cell, and cell manufacturing process.
El invento se refiere a una célula de conmutación de potencia así como a un procedimiento de fabricación de esta célula.The invention relates to a cell of power switching as well as a manufacturing procedure of this cell.
Más precisamente, el invento se refiere a una célula de conmutación que comprende:More precisely, the invention relates to a switching cell comprising:
- al menos dos componentes de potencia que representan cada uno una primera cara equipada de al menos un borne de conexión eléctrica y una segunda cara opuesta equipada de al menos otro borne de conexión eléctrica formando éstos componentes una cadena de componentes eléctricamente conectados en serie por medio de al menos una conexión intermedia uniendo eléctricamente cada conexión intermedia la segunda cara del componente precedente a la primera cara del componente siguiente en dicha cadena, y- at least two power components that each one represents a first face equipped with at least one terminal of electrical connection and a second opposite face equipped with al minus another electrical connection terminal forming these components a chain of components electrically connected in series by means of at least one intermediate connection electrically joining each intermediate connection the second face of the preceding component a the first face of the next component in said chain, and
- un sustrato dieléctrico en el interior del cual están incorporados al menos dichos dos componentes.- a dielectric substrate inside the which are incorporated at least said two components.
Tales células de conmutación son, por ejemplo, frecuentemente utilizadas para realizar onduladores destinados a alimentar motores eléctricos utilizados para la tracción de los trenes. En tales aplicaciones, la célula de conmutación debe ser capaz de conmutar corrientes superiores a mil amperios y de resistir tensiones superiores a cinco mil voltios. Para alcanzar tales prestaciones y en particular para soportar tales pensiones como cada célula de conmutación está realizada a partir de varios interruptores elementales tales como transistores IGBT, conectados unos a otros en serie.Such switching cells are, for example, frequently used to make inverters intended for power electric motors used for traction of trains In such applications, the switching cell must be capable of switching currents greater than one thousand amps and resisting voltages higher than five thousand volts. To achieve such benefits and in particular to support such pensions as each switching cell is made from several elemental switches such as IGBT transistors, connected each other in series.
Por otra parte, hoy el CPES (Centro para Sistemas Electrónicos de Potencia (CPES), Virginia Tech., 657 Whittemore Hall (0111) Blacksburg, VA 24061) ha divulgado un procedimiento para incorporar transistores que trabajan a menos de 600 voltios, en el interior de un sustrato. Por ejemplo en el artículo "tecnología de Empaquetado de Integración de Potencia Embebida para IPEM" por los autores Zhenxian Liang, Fred C. Lee, y G.Q. Lu, del que se puede obtener una copia en el CPES, un primer transistor IGBT1, y un segundo transistor IGBT2 conectados en serie están los dos incorporados en el espesor de una lámina horizontal de material dieléctrico. La cara superior de cada uno de estos transistores, equipada de bordes de conexión de rejilla y de emisor, está vuelta hacia arriba, mientras que la cara inferior, equipada de un borne de conexión del colector, está vuelta hacia abajo. Para conectar estos dos transistores en serie, es por tanto necesario conectar eléctricamente, por ejemplo el emisor del transistor IGBT1 al colector del transistor IGBT2. Esta unión es aquí denominada conexión intermedia. Ya que el emisor del transistor IGBT1 está sobre la cara superior de la lámina mientras que el colector del transistor IGBT2 está sobre la cara inferior de la lámina, esta unión debe atravesar el sustrato. Existen por tanto sobre la superficie superior de la lámina al menos dos potenciales diferentes Ve1 y Ve2 correspondiente respectivamente a los potenciales de los emisores de los transistores IGBT1 e IGBT2. Igualmente, sobre la cara inferior de la lámina existen igualmente dos potenciales diferentes Vc1 y Vc2 correspondientes respectivamente a los potenciales de los colectores de los transistores IGBT1 e IGBT2. Ya que estos dos transistores están conectados en serie, la tensión Ve1 es igual a la tensión Vc2.On the other hand, today the CPES (Center for Electronic Power Systems (CPES), Virginia Tech., 657 Whittemore Hall (0111) Blacksburg, VA 24061) has disclosed a procedure to incorporate transistors that work at less than 600 volts, inside a substrate. For example in the Article "Power Integration Packaging technology Embedded for IPEM "by the authors Zhenxian Liang, Fred C. Lee, and G.Q. Lu, from which you can get a copy in the CPES, a first IGBT1 transistor, and a second IGBT2 transistor connected in series the two are incorporated in the thickness of a horizontal sheet of dielectric material The upper face of each of these transistors, equipped with grid and emitter connection edges, is turned up, while the lower face, equipped of a collector connection terminal, it is turned down. For connect these two transistors in series, it is therefore necessary connect electrically, for example the transmitter of the transistor IGBT1 to the IGBT2 transistor collector. This union is called here intermediate connection Since the emitter of transistor IGBT1 is on the upper face of the sheet while the collector of the IGBT2 transistor is on the underside of the sheet, this union must pass through the substrate. They exist therefore on the top sheet surface at least two different potentials Ve1 and Ve2 corresponding respectively to the potentials of the emitters of the transistors IGBT1 and IGBT2. Likewise, about lower side of the sheet there are also two potentials different Vc1 and Vc2 corresponding respectively to the potentials of the collectors of the IGBT1 and IGBT2 transistors. Already that these two transistors are connected in series, the voltage Ve1 is equal to the voltage Vc2.
La presencia de diferentes potenciales sobre la misma cara del sustrato impone espaciar el primer y segundo transistores uno del otro en una distancia mínima de aislamiento. Por debajo de esta distancia mínima de aislamiento un cortocircuito corre el riesgo de establecerse entre estos dos potenciales, ya sea por ruptura dieléctrica del aire circundante, ya sea por encaminamiento a la superficie del sustrato. Esta distancia de aislamiento es por tanto función a la vez de las propiedades dieléctricas del aire y del valor de los diferentes potenciales.The presence of different potentials on the same face of the substrate imposes space the first and second transistors from each other in a minimum isolation distance. Below this minimum isolation distance a short circuit You run the risk of establishing yourself between these two potentials, either by dielectric breakdown of the surrounding air, either by routing to the substrate surface. This distance from isolation is therefore a function of both properties dielectrics of the air and the value of the different potentials.
Por consiguiente, cuando se desea aplicar esta tecnología para realizar células de conmutación de potencia capaces de trabajar bajo tensiones de varios miles de voltios, la distancia mínima de aislamiento a respetar aumenta y el volumen de la célula de conmutación también. Esto es un freno a la aplicación de la enseñanza del artículo del CPES en el dominio de las tensiones medias.Therefore, when you want to apply this technology to perform power switching cells capable of working under voltages of several thousand volts, the distance minimum insulation to respect increases and the cell volume switching too. This is a brake on the application of the teaching of the CPES article in the domain of tensions socks.
Así, el invento pretende mejorar las técnicas de integración de componentes desarrolladas por el CPES de manera que pueda aplicar esta tecnología a componentes de potencia en el dominio de las tensiones medias.Thus, the invention aims to improve the techniques of integration of components developed by the CPES so that can apply this technology to power components in the mastery of medium tensions.
El invento tiene por tanto por objeto una célula de conmutación de potencia tal como se ha descrito anteriormente, caracterizada:The object of the invention is therefore a cell of power switching as described above, characterized:
- porque la o cada conexión intermedia así como las caras de los componentes conectados a esta conexión intermedia están totalmente incorporadas al interior de dicho sustrato, y- because the or each intermediate connection as well as the faces of the components connected to this intermediate connection are fully incorporated into said substrate, and
- porque las caras no conectadas a una conexión intermedia de los componentes situados en las extremidades de dicha cadena están dispuestas de manera que este separadas unas de la otra por medio del material dieléctrico que forma dicho sustrato en el que están incorporados. Los cortocircuitos por encaminamiento a la superficie del sustrato no existen por tanto ya.- because faces not connected to a connection intermediate of the components located at the ends of said chain are arranged so that it is separated from each other by means of the dielectric material that forms said substrate in the They are incorporated. Short circuits by routing to the Substrate surface does not exist therefore.
En la célula anterior, el potencial de cada conexión intermedia está aislado de los potenciales diferentes presentes en otros puntos de la misma cadena por medio del material dieléctrico que forma el sustrato en el que éstos componentes están incorporados. Los cortocircuitos por encaminamiento a la superficie del sustrato no existen por tanto ya.In the previous cell, the potential of each intermediate connection is isolated from the different potentials present in other points of the same chain through the material dielectric that forms the substrate in which these components are incorporated. Short circuits by routing to the surface of the substrate do not exist therefore.
Este material dieléctrico presenta una resistencia a la tensión de ruptura superior a la del aire de manera que la distancia mínima a prever entre dos componentes sucesivos de dicha cadena puede ser reducida. Por consiguiente, incorporando además en el sustrato la conexión intermedia, resulta posible aplicar la enseñanza del artículo del CPES a componentes de potencia destinados a trabajar en las tensiones medias obteniendo el mismo tiempo una célula cuyo volumen permanece razonable.This dielectric material has a breaking stress resistance greater than that of air so that the minimum distance to be foreseen between two successive components of said chain can be reduced. Therefore, incorporating also in the substrate the intermediate connection is possible apply the teaching of the CPES article to components of power destined to work in the medium tensions obtaining the at the same time a cell whose volume remains reasonable.
Según otras características de una célula conforme a la mención:According to other characteristics of a cell according to the mention:
- las caras no conectadas a una conexión intermedia de los componentes situados en las extremidades de dicha cadena están vueltas en direcciones diferentes de manera que el camino más corto entre estas dos caras atraviese el material dieléctrico que forma dicho sustrato en el que están incorporados;- faces not connected to a connection intermediate of the components located at the ends of said string are turned in different directions so that the shortest path between these two faces through the material dielectric forming said substrate on which they are incorporated;
- el sustrato está formado por un apilamiento de láminas paralelas de material dieléctrico, y porque cada uno de los componentes que se siguen en dicha cadena está incorporado en el espesor de una lámina diferente;- the substrate is formed by a stack of parallel sheets of dielectric material, and because each of the components that are followed in that chain is incorporated into the thickness of a different sheet;
- la primera y segunda caras de cada componente son paralelas a las caras de la lámina en la que el componente está incorporado;- the first and second faces of each component are parallel to the faces of the sheet in which the component is Incorporated;
- al menos una de las primera y segunda caras de cada componente aflora por un lado de la lámina en la que el componente está incorporado;- at least one of the first and second faces of each component emerges from one side of the sheet in which the component is incorporated;
- dicha conexión intermedia entre dos componentes está formada por una pista eléctrica grabada en al menos una de las caras de la lámina en la que uno de estos dos componentes está incorporado;- said intermediate connection between two components is formed by an electric track recorded in at least one of the faces of the sheet in which one of these two components is incorporated;
- al menos uno de los dos componentes de dicha cadena está soldado sobre dicha pista eléctrica grabada;- at least one of the two components of said chain is welded on said recorded electric track;
- comprende al menos un canal de circulación de un fluido de refrigeración previsto en el interior de dicho sustrato para enfriar al menos uno de los componentes incorporados en este sustrato;- comprises at least one circulation channel of a cooling fluid provided inside said substrate to cool at least one of the incorporated components in this substrate;
- comprende varios canales de circulación de un fluido de refrigeración, y cada componente de potencia está interpuesto entre al menos dos de estos canales de manera que su primera y su segunda cara sean refrigeradas por estos canales;- comprises several circulation channels of a cooling fluid, and each power component is interposed between at least two of these channels so that your first and second faces are cooled by these channels;
- comprende al menos un canal de circulación de un fluido de refrigeración previsto en cada lámina que forma dicho sustrato;- comprises at least one circulation channel of a cooling fluid provided on each sheet that forms said substratum;
- al menos dicho canal previsto en cada lámina está situado por debajo del o de cada componente soldado sobre la cara de esta lámina;- at least said channel provided in each sheet is located below the or of each welded component on the face of this sheet;
- el sustrato presenta al menos una primera y una segunda caras opuestas; la célula comprende una lengüeta de conexión eléctrica conectadas a la primera cara del primer componente, de dicha cadena y una segunda lengüeta de conexión eléctrica conectada a la segunda cara del último componente de dicha cadena, y la primera y segunda lengüetas sobresalen respectivamente sobre la primera y segunda caras opuestas;- the substrate has at least one first and a second opposite faces; the cell comprises a tongue of electrical connection connected to the first face of the first component, of said chain and a second connection tab electric connected to the second face of the last component of said string, and the first and second tabs protrude respectively on the first and second opposite faces;
- el sustrato presenta una tercera cara diferente de la primera y segunda caras, la célula comprende al menos una tercera lengüeta de conexión eléctrica conectada a una conexión intermedia y esta tercera lengüeta sobresale a partir de la primera cara;- the substrate has a third face different from the first and second faces, the cell comprises the minus a third electrical connection tab connected to a intermediate connection and this third tongue protrudes from the first face;
- los componentes son transistores de potencia; y- the components are power transistors; Y
- el sustrato es de forma paralelepípedica;- the substrate is parallelepipedic;
- las láminas que incorporan los componentes son todas de tamaño idéntico.- the sheets that incorporate the components are All of identical size.
El invento tiene igualmente por objeto un procedimiento de fabricación de una célula de conmutación conforme el invento que comprende:The invention also has as its object a manufacturing process of a conforming switching cell the invention comprising:
- una fase de fabricación de bloques elementales, estando formado cada bloque elemental por una lámina del sustrato sobre la que está soldado uno de los componentes de potencia y en la que hay previsto un agujero pasante destinado a recibir el componente de potencia de otro bloque elemental idéntico, y- a block manufacturing phase elementary, each elementary block being formed by a sheet of the substrate on which one of the components of power and in which there is a through hole intended for receive the power component of another identical elementary block, Y
- una fase de ensamblaje durante la cual los bloques elementales son apilados unos sobre otros para formar dicha célula de conmutación.- an assembly phase during which elementary blocks are stacked on each other to form said switching cell
El documento US2003/0090873 describe una célula de conmutación que comprende un apilamiento de varios módulos de potencia que están separados uno de otro por un espaciamiento para recibir un líquido de refrigeración. El dispositivo según el presente invento es ventajoso con relación a este dispositivo porque permite un mayor grado de integración.US2003 / 0090873 describes a cell switching comprising a stack of several modules of power that are separated from each other by a spacing for Receive a cooling liquid. The device according to The present invention is advantageous in relation to this device because It allows a greater degree of integration.
El invento será mejor comprendido con la lectura de la descripción siguiente, dado únicamente a título de ejemplo y hecha con referencia a los dibujos en los que:The invention will be better understood with reading of the following description, given by way of example only and made with reference to the drawings in which:
La fig. 1 es un esquema eléctrico de una cadena de tres componentes de potencia;Fig. 1 is an electrical scheme of a chain three power components;
La fig. 2 es una ilustración esquemática en perspectiva de una célula de conmutación conforme el invento,Fig. 2 is a schematic illustration in perspective of a switching cell according to the invention,
Las figs. 3 y 4 son vistas en corte respectivamente según las líneas III-III y IV-IV de la célula de conmutación de la fig. 2.Figs. 3 and 4 are views in section respectively according to lines III-III and IV-IV of the switching cell of fig. 2.
La fig. 5 es un organigrama de un procedimiento de fabricación de la célula de la fig. 1,Fig. 5 is a flow chart of a procedure of manufacturing the cell of fig. one,
Las figs. 6A a 6F son ilustraciones esquemáticas de la célula de la fig. 2 en diferentes estadios de fabricación.Figs. 6A to 6F are schematic illustrations of the cell of fig. 2 in different manufacturing stages.
La fig. 1 representa una cadena 2 formada por tres transistores IGBT (Transistor Bipolar de Puerta Aislada) 4, 5 y 6 conectados en serie entre un potencial de entrada Ve y un potencial de salida Vs. El emisor del transistor 4 está conectado al potencial Ve mientras que el colector del transistor 6 está conectado al potencial Vs. Conexiones intermedias 7 y 8 conectan directamente, de modo respectivo el emisor del transistor 5 al colector del transistor 4 y el emisor del transistor 6 al colector de transistor 5.Fig. 1 represents a chain 2 formed by three transistors IGBT (Bipolar Transistor of Isolated Door) 4, 5 and 6 connected in series between an input potential See and a output potential Vs. The emitter of transistor 4 is connected to potential See while the collector of transistor 6 is connected to potential Vs. Intermediate connections 7 and 8 connect directly, respectively the emitter of transistor 5 to collector of transistor 4 and emitter of transistor 6 to the collector of transistor 5.
Tres diodos 10, 11 y 12, están conectados cada uno en posición anti-paralela a los bornes respectivamente de los transistores 4, 5 y 6. Está cadena corresponde, por ejemplo, al esquema eléctrico de una célula de conmutación destinada a formar uno de los dos interruptores de uno de los brazos de un ondulador trifásico apropiado para alimentar motores eléctricos de tracción de un tren.Three diodes 10, 11 and 12, are connected each one in anti-parallel position to the terminals respectively of transistors 4, 5 and 6. This chain is corresponds, for example, to the electrical scheme of a cell of switching intended to form one of the two switches of one of the arms of a three-phase inverter suitable for feeding electric motors of traction of a train.
La fig. 2 representa una célula de conmutación, designada por la referencia general 20, correspondiente el esquema eléctrico de la fig. 1.Fig. 2 represents a switching cell, designated by general reference 20, corresponding scheme electric of fig. one.
Esta célula está formada por un sustrato 22 de material dieléctrico de forma sensiblemente paralelepipédica en el interior del cual están incorporados los transistores 4 a 6 y los diodos 10 a 12 de la fig. 1. El sustrato 22 está formado por un apilamiento de 4 láminas horizontales 24 a 27 de material dieléctrico y térmicamente conductor tal como aluminio, nitruro de aluminio o diamante. En el interior de cada lámina 25 a 27 están incorporados un transistor y su diodo anti-paralelo. Más precisamente, las láminas 25, 26 y 27 incorporan respectivamente el transistor 6 y su diodo 12, el transistor 5 y su diodo 11, y el transistor 4 y su diodo 10.This cell is formed by a substrate 22 of dielectric material of substantially parallelepipedic form in the inside of which transistors 4 to 6 are incorporated and the diodes 10 to 12 of fig. 1. The substrate 22 is formed by a stacking of 4 horizontal sheets 24 to 27 of material dielectric and thermally conductive such as aluminum, nitride aluminum or diamond Inside each sheet 25 to 27 are incorporated a transistor and its diode anti-parallel More precisely, sheets 25, 26 and 27 respectively incorporate transistor 6 and its diode 12, the transistor 5 and its diode 11, and transistor 4 and its diode 10.
Cada lámina 24 a 27 tiene la forma de un paralelepípedo rectángulo sobre la cara superior del cual están grabadas pistas eléctricas que serán descritas más en detalle con referencia a la fig. 3. En la cara inferior de cada una de estas láminas 24 a 27 hay previsto un grupo, respectivamente 30 a 33, de canales de circulación de un fluido de refrigeración. Estos canales atraviesan de parte a parte el sustrato 22 a partir de la cara delantera hasta la cara trasera del paralelepípedo y se extienden paralelamente a las caras del lado del sustrato 22. Aquí, cada grupo comprende ocho canales espaciados uno del otro en 2 mm y de una profundidad de 0,5 mm.Each sheet 24 to 27 has the shape of a parallelepiped rectangle on the upper face of which they are recorded electric tracks that will be described in more detail with reference to fig. 3. On the underside of each of these plates 24 to 27 there is a group, respectively 30 to 33, of Circulation channels of a cooling fluid. These channels cross the substrate 22 from part to side from the face front to the back face of the parallelepiped and extend parallel to the sides of the substrate side 22. Here, each group comprises eight channels spaced apart from each other in 2 mm and of a depth of 0.5 mm.
Aquí, lengüetas de conexión 36 a 38 conectadas respectivamente a las rejillas de los transistores 4 a 6 sobresalen horizontalmente hacia el exterior a partir de la cara anterior del sustrato 22.Here, connection tabs 36 to 38 connected respectively to transistor grids 4 to 6 protrude horizontally outward from the front face of the substrate 22.
La célula 20 comprende igualmente lengüetas 42 y 44 de conexión de potencia respectivamente conectadas al colector del transistor 6 y al emisor del transistor 4. Estas lengüetas 42 y 44 sobresalen hacia el exterior a partir de las caras opuestas del sustrato 22, es decir aquí la cara vertical del lado izquierdo y la cara vertical del lado derecho del sustrato 22.Cell 20 also comprises tabs 42 and 44 power connection respectively connected to the collector from transistor 6 and to emitter of transistor 4. These tabs 42 and 44 protrude outward from opposite sides of the substrate 22, that is here the vertical face of the left side and the vertical face of the right side of the substrate 22.
Las lengüetas 36 a 38 están destinadas a ser conectadas a una unidad de mando de la conmutación de los transistores 4 a 6. Las lengüetas 42 y 44 está en cuanto a ellas destinadas respectivamente a ser conectadas a los potenciales Vs y Ve.Tabs 36 to 38 are intended to be connected to a switching control unit of the transistors 4 to 6. Tabs 42 and 44 are as for them destined respectively to be connected to the potentials Vs and Go.
Finalmente, interpuestas entre cada lámina, el sustrato 22 comprende capas de unión destinadas a fijar rígidamente las láminas entre sí, que serán descritas de manera más detallada con referencia a la fig. 4.Finally, interposed between each sheet, the substrate 22 comprises tie layers intended to rigidly fix the sheets together, which will be described in more detail with reference to fig. Four.
La fig. 3 representa una vista desde arriba de la cara superior de la lámina 25.Fig. 3 represents a view from above of the upper face of the sheet 25.
Los dos cuadrados en trazos representan respectivamente el emplazamiento donde son incorporados en esta lámina 25 el transistor 6 y el diodo anti-paralelo 12.The two squares in strokes represent respectively the location where they are incorporated into this sheet 25 transistor 6 and anti-parallel diode 12.
Sobre esta cara superior, dos pistas eléctricas 50 y 52, por ejemplo de cobre, están grabadas. La pista 50 se prolonga a partir de un punto 54 de conexión a la rejilla del transistor 6 hasta un punto de conexión con la lengüeta 36.On this upper face, two electric tracks 50 and 52, for example copper, are engraved. Track 50 is extends from a connection point 54 to the grid of the transistor 6 to a connection point with the tongue 36.
La pista 52 está destinada a conectar el emisor del transistor 6 y el ánodo del diodo 12 al colector de transistor 5 y al cátodo del diodo 11 para formar la conexión intermedia 8. A este efecto, la pista 52 extiende a partir de puntos 56 de conexión al emisor del transistor 6 y de puntos 58 de conexión al ánodo del diodo 12. La pista 52 presenta por otra parte, una superficie suficientemente extensa para que el colector del transistor 5 pueda ser soldado sobre esta así como el cátodo del diodo 11. La superficie de la pista 52 es elegida tan grande como sea posible para difundir y disipar el calor del transistor 5.Track 52 is intended to connect the transmitter from transistor 6 and anode of diode 12 to transistor manifold 5 and to the cathode of diode 11 to form the intermediate connection 8. A this effect, track 52 extends from connection points 56 to the emitter of transistor 6 and connection points 58 to the anode of the diode 12. Track 52 also has a surface extensive enough so that the collector of transistor 5 can be a soldier on this as well as the cathode of diode 11. The runway surface 52 is chosen as large as possible to diffuse and dissipate the heat of the transistor 5.
De manera similar a lo que se ha descrito para la lámina 25, unas pistas eléctricas están grabadas sobre cada una de las caras superiores de las láminas 24, 26 y 27 de manera que formen las conexiones eléctricas de la cadena 2. Estas pistas eléctricas serán descritas más en detalle con respecto a la fig. 4.Similar to what has been described for sheet 25, electric tracks are engraved on each of the upper faces of sheets 24, 26 and 27 so that form the electrical connections of the chain 2. These tracks electrical will be described in more detail with respect to fig. Four.
La fig. 4 representa un corte vertical según la línea IV-IV del sustrato 22.Fig. 4 represents a vertical cut according to the line IV-IV of the substrate 22.
En la estructura de la célula 1, cada transistor 4, 5, 6 está incorporado en una lámina de material dieléctrico, por ejemplo poniendo en práctica el procedimiento descrito en el artículo del CPES precedentemente referenciado.In the structure of cell 1, each transistor 4, 5, 6 is incorporated in a sheet of dielectric material, by example implementing the procedure described in the CPES article previously referenced.
Los componentes de potencia incorporados en estas láminas presentarán cada uno una cara superior y una cara inferior equipadas de bornes de conexión respectivos. Por ejemplo en el caso de los transistores 4, 5 y 6, la cara superior comprende un borne 60 de conexión a la rejilla del transistor y seis bornes 62 de conexión al emisor del transistor. Sobre esta vista en corte, sólo son visibles dos bornes 62 para cada transistor.The power components incorporated in these sheets will each have a top face and a face bottom equipped with respective connection terminals. For example in In the case of transistors 4, 5 and 6, the upper face comprises a terminal 60 connecting to the transistor grid and six terminals 62 of Transistor emitter connection. On this view in court, only two terminals 62 are visible for each transistor.
La cara inferior de cada transistor comprende un borne 64 de conexión del colector del transistor que se extiende sensiblemente sobre toda la superficie inferior del transistor.The underside of each transistor comprises a terminal 64 connecting the transistor manifold that extends substantially over the entire lower surface of the transistor.
De manera similar los diodos 10 a 12 se presentan en forma de un componente que presenta una cara superior que lleva tres bornes de conexión del ánodo y una cara inferior que lleva un borne de conexión del cátodo (no representado). Sólo la conexión de los transistores entre sí está representada en detalle en la fig. 4. La conexión de los diodos en serie es similar a la de los transistores y se deduce de las explicaciones dadas a continuación.Similarly diodes 10 to 12 are present in the form of a component that has an upper face which has three anode connection terminals and a lower face that It has a cathode connection terminal (not shown). Only the connection of the transistors to each other is represented in detail in fig. 4. The connection of the diodes in series is similar to that of the transistors and it follows from the explanations given to continuation.
Un transistor y su diodo conectado en posición anti paralelo incorporados en la misma lámina forman un grupo de componentes. Estos grupos están dispuestos alternativamente a derecha e izquierda de un plano vertical medio 72 de manera que sea posible disponer un grupo de canales de circulación de un fluido de refrigeración por debajo de cada grupo sucesivo en la cadena 2. El plano 72 es perpendicular al plano de la fig. 4. Aquí, los transistores 46 están dispuestos a la izquierda de este plano mientras que transistor 5 está dispuesto a la derecha.A transistor and its diode connected in position anti parallel incorporated in the same sheet form a group of components. These groups are alternately willing to right and left of a medium vertical plane 72 so that it is it is possible to arrange a group of circulation channels of a fluid of cooling below each successive group in chain 2. The plane 72 is perpendicular to the plane of fig. 4. Here, the transistors 46 are arranged to the left of this plane while transistor 5 is arranged on the right.
Sobre la cara superior de la lámina 24 está grabada una pista eléctrica 68 sobre la que el colector 64 del transistor 6 y el cátodo del diodo 12 están soldados con soldadura dura. Esta pista 68 está igualmente conectada por soldadura dura o por soldadura blanda a la lengüeta 42.On the upper face of the sheet 24 is recorded an electric track 68 on which the collector 64 of the transistor 6 and diode cathode 12 are welded hard. This track 68 is also connected by hard welding or by soft welding to tongue 42.
Ningún componente de potencia está incorporado en esta lámina 24 situada en la extremidad inferior del apilamiento.No power component is incorporated in this sheet 24 located at the lower end of the stacking
El colector 64 del transistor 5 y el cátodo del diodo 11 están soldados con soldadura dura sobre la pista 52 de la lámina 25 a la derecha del plano 72.The collector 64 of transistor 5 and the cathode of diode 11 are welded with hard solder on track 52 of the sheet 25 to the right of plane 72.
El colector 64 del transistor 4 y el cátodo del diodo 10 está soldados por soldadura duda sobre una pista 70 grabada sobre la cara superior de la lámina 26. La cara superior de la lámina 26 es la simétrica de la cara superior de la lámina 25 con relación al plano 72 de tal manera que la pista 70 forme la conexión intermedia 7.The collector 64 of transistor 4 and the cathode of diode 10 is welded by welding doubt on a track 70 engraved on the upper face of the sheet 26. The upper face of sheet 26 is symmetrical of the upper face of sheet 25 in relation to plane 72 such that track 70 forms the intermediate connection 7.
La cara superior de la lámina 27 situada en la extremidad superior del apilamiento es idéntica a la lámina 26 con la excepción del hecho de que la pista conectada al emisor del transistor 4 está igualmente conectada a la lengüeta 44 y de que ningún transistor o diodo está soldado con soldadura dura sobre esta cara.The upper face of the sheet 27 located in the upper extremity of the stack is identical to sheet 26 with the exception of the fact that the track connected to the transmitter of the transistor 4 is also connected to tongue 44 and that no transistor or diode is welded with hard solder on this face.
Cada grupo de canales 30 a 33 está aquí ahuecado en la lámina correspondiente a partir de la cara inferior de ésta situada justo por debajo del lugar donde están soldados sobre su cara superior el transistor y el diodo.Each group of channels 30 to 33 is here hollowed out in the corresponding sheet from the underside of it located just below the place where they are soldiers on their upper face the transistor and the diode.
A título de ilustración, las láminas 24 a 27 son todas de espesor constante igual a 1 mm o más y los transistores 4 se son todos idénticos y presentan un espesor de aproximadamente 500 micras. El espesor de las pistas 52, 68 y 70 es aquí de 100 micras.By way of illustration, plates 24 to 27 are all of constant thickness equal to 1 mm or more and transistors 4 they are all identical and have a thickness of approximately 500 microns The thickness of tracks 52, 68 and 70 is here 100 microns
Cada transistor y diodo son alojados en agujeros 73 respectivos que atraviesan la lámina en la que están incorporados. En el interior de sus agujeros respectivos, el transistor y el diodo están dispuestos de manera que el borne 64, respectivamente el cátodo, aflore paralelamente a la cara inferior de esta lámina. Por el contrario, los bornes 60 y 62 del transistor, respectivamente el ánodo del diodo, están situados en un plano paralelo a la cara superior pero situado por debajo del nivel de la cara superior de manera que los bornes 60 y 62 así como el ánodo estén enteramente incorporados en el interior de la lámina. Los transistores y los diodos están fijados en esta posición con ayuda de una resina aislante 74 dispuesta entre la superficie exterior del transistor y del diodo y la superficie interior de los agujeros 73 en los que están alojados.Each transistor and diode are housed in holes 73 respective that cross the sheet in which they are incorporated. Inside their respective holes, the transistor and diode are arranged so that terminal 64, respectively the cathode, emerge parallel to the lower face of this sheet. On the contrary, terminals 60 and 62 of the transistor, respectively the anode of the diode, are located in a plane parallel to the upper face but below the level of the upper face so that terminals 60 and 62 as well as the anode are entirely incorporated inside the sheet. The transistors and diodes are fixed in this position with support of an insulating resin 74 disposed between the surface outside of the transistor and diode and the inside surface of the holes 73 in which they are housed.
Esta resina aislante 74 está igualmente extendida entre dos láminas sucesivas del apilamiento de manera que aísle eléctricamente las pistas 52, 68 y 70 así como los puntos de conexión 54, 56 del entorno exterior. En particular, este deposito de resina aislante asegura el aislamiento eléctrico entre los puntos de conexión 54 y 56 y los grupos de canales de circulación de fluido de refrigeración.This insulating resin 74 is also extended between two successive sheets of the stack so that electrically isolate tracks 52, 68 and 70 as well as the points of connection 54, 56 from the outside environment. In particular, this deposit Insulating resin ensures electrical insulation between points connection 54 and 56 and the circulation channel groups of cooling fluid
Para cada transistor y diodo incorporados en una lámina, los puntos de conexión 54, 56 y 58 están formados por un depósito de material conductor entre por una parte los bornes de conexión sobre la cara superior del transistor o del diodo y por otra parte las pistas correspondientes grabadas sobre la cara superior de esta lámina.For each transistor and diode incorporated in a sheet, the connection points 54, 56 and 58 are formed by a deposit of conductive material between the terminals of connection on the upper face of the transistor or diode and by other part the corresponding tracks recorded on the face top of this sheet.
Cada punto de conexión comprende una parte rectilínea vertical correspondiente a un pozo relleno de material conductor. Aquí, un pozo 82 está formado entre la cara superior de la lámina en la que está incorporado un transistor y los bornes de conexión 62 de este transistor. De manera similar, un pozo 80 está formado entre la cara superior de cada lámina que incorpora un transistor y el borne de conexión 60 de la rejilla de este transistor.Each connection point comprises a part vertical rectilinear corresponding to a well filled with material driver. Here, a well 82 is formed between the upper face of the sheet in which a transistor is incorporated and the terminals of connection 62 of this transistor. Similarly, a well 80 is formed between the upper face of each sheet that incorporates a transistor and terminal 60 of the grid of this transistor.
Un procedimiento de fabricación de la célula de conmutación 20 va a ser descrito a continuación con relación al procedimiento de la fig. 5 y de las figs. 6A a 6F en el caso particular de una célula de conmutación que comprende tres transistores conectados en serie.A manufacturing process of the cell switching 20 will be described below in relation to the procedure of fig. 5 and of figs. 6A to 6F in the case particular of a switching cell comprising three series connected transistors.
El procedimiento se desarrolla en dos fases principales. En primer lugar una fase 100 de fabricación de bloques elementales estándares seguida de una fase 102 de ensamblaje de estos bloques elementales para formar la célula 20.The procedure takes place in two phases. main. First a block manufacturing phase 100 standard elementals followed by an assembly phase 102 of these elementary blocks to form cell 20.
Durante la fase 100 unos bloques de base correspondientes a la lámina 24 asociada al transistor 6 y al diodo 12, son fabricados durante una etapa 104.During the 100 phase some basic blocks corresponding to sheet 24 associated with transistor 6 and diode 12, are manufactured during a stage 104.
Durante esta etapa 104, un soporte convencional de componentes eléctricos es cortado, durante una operación 105, a un formato estándar. Tal soporte convencional se presenta en forma de una capa de material dieléctrico que presenta una cara superior de cobre destinada a ser grabada. A continuación, el grupo 30 de canales es ahuecado, durante una operación 106, sobre la cara inferior del soporte.During this step 104, a conventional support of electrical components is cut, during an operation 105, to a standard format Such conventional support comes in the form of a layer of dielectric material having an upper face of copper destined to be engraved. Next, group 30 of channels is hollowed out, during an operation 106, on the face bottom bracket.
La superficie de cobre de la placa es grabada, durante una operación 108, para formar la pista 68 y el transistor 6 y el diodo 12 son soldados con soldadura dura durante una operación 110 sobre la pista 68. Durante la operación 110, la lengüeta 42 es igualmente soldada con la pista 68.The copper surface of the plate is engraved, during an operation 108, to form track 68 and the transistor 6 and diode 12 are welded with hard solder during a operation 110 on runway 68. During operation 110, the tongue 42 is also welded with track 68.
A la salida de estas operaciones 106 a 110, es obtenido el ladrillo de base representado en corte longitudinal en la fig. 6A.At the exit of these operations 106 to 110, it is obtained the base brick represented in longitudinal section in fig. 6A.
Simultáneamente a esta etapa 104, es realizada una etapa 116 de fabricación de ladrillos intermedios. Esta etapa 116 comprende las mismas operaciones que la etapa 104 así como una operación suplementaria 114 consistente en cortar en el soporte los dos agujeros 73 destinados a recibir cada uno un transistor o un diodo. Estos agujeros atraviesan de parte a parte el espesor del soporte y están previstos por el lado opuesto a aquél en que el transistor y el diodo son soldados con soldadura dura. Durante la operación 110 de la etapa 116, ninguna lengüeta 42 es soldada.Simultaneously to this stage 104, it is performed a step 116 of intermediate brick manufacturing. This stage 116 comprises the same operations as step 104 as well as a supplementary operation 114 consisting of cutting the two holes 73 each intended to receive a transistor or a diode. These holes pass through the thickness of the support and are provided on the opposite side to that on which the Transistor and diode are welded with hard welding. During the step 110 operation 116, no tongue 42 is welded.
Así, a la salida de la etapa 116, se obtiene un ladrillo intermedio representado en la fig. 6B correspondiente por ejemplo a la lámina 25 asociada al transistor 5 de la fig. 4.Thus, at the exit of step 116, a intermediate brick shown in fig. 6B corresponding by example to sheet 25 associated with transistor 5 of fig. Four.
Igualmente en paralelo a las etapas 104 y 116, una etapa 118 de fabricación de ladrillos de extremidad destinados a ser colocados en la extremidad superior del apilamiento de láminas es realizada. Esta etapa 118 es idéntica a la etapa 104 con la excepción del hecho de que la etapa 110 es reemplazada por la etapa 114 y de que una operación 119 de conexión de la lengüeta de conexión 44 es realizada. A la salida de esta etapa 118, un ladrillo de extremidad similar a la lámina 27 asociado a la lengüeta 44 es obtenido.Also in parallel to steps 104 and 116, a stage 118 of fabrication of tip bricks intended to be placed in the upper extremity of the sheet stacking It is done. This stage 118 is identical to step 104 with the exception to the fact that stage 110 is replaced by stage 114 and that an operation 119 of connecting the tongue of connection 44 is made. At the exit of this stage 118, a brick similar to the blade 27 associated with the tongue 44 is obtained.
Durante esta fase 101 gran cantidad de ladrillos elementales son fabricados y almacenados sin presagiar, en este estado de la fabricación, si estos ladrillos elementales serán a continuación utilizados para fabricar células de conmutación que llevan 2, 3, 4 o más, transistores en serie.During this phase 101 large amount of bricks Elementals are manufactured and stored without presage, in this manufacturing status, if these elementary bricks will be to then used to make switching cells that They carry 2, 3, 4 or more, series transistors.
Durante la fase 102, una capa de la resina aislante 74 es depositada, durante una etapa 120, sobre la cara superior de ladrillo de base de manera que aísle eléctricamente la pista 68 del entorno exterior. En particular, esta capa está destinada a aislar eléctricamente la pista 68 del grupo de canales 31.During phase 102, a resin layer insulator 74 is deposited, during a step 120, on the face top brick base so that it electrically insulates the track 68 of the outside environment. In particular, this layer is intended to electrically isolate track 68 from the channel group 31.
Una vez que ha terminado esta etapa 120, es repartida cola (no representada) durante una etapa 121, sobre la cara superior del ladrillo de base. Esta cola es dispuesta de manera que asegure la fijación sobre esta cara superior de un ladrillo intermedio.Once this stage 120 is over, it is distributed tail (not shown) during a step 121, on the upper face of the base brick. This tail is arranged so that ensures the fixation on this upper face of a brick intermediate.
A continuación, un ladrillo intermedio es apilado, durante una etapa 122, sobre el ladrillo de base de tal manera que el transistor soldado con soldadura dura sobre el ladrillo de base sea alojado en el interior del agujero 73 previsto en el ladrillo intermedio.Next, an intermediate brick is stacked, during a step 122, on the base brick of such so that the welded welded transistor lasts on the base brick be housed inside the hole 73 provided In the middle brick.
A la salida de la etapa 122, es obtenido el ensamblaje de la fig. 6C, correspondiendo este ensamblaje por ejemplo al apilamiento de la lámina 25 sobre la lámina 24.At the exit of step 122, the assembly of fig. 6C, this assembly corresponding by example of stacking sheet 25 on sheet 24.
La resina 74 de material dieléctrico aislante tal como una resina epoxídica, es depositada, durante una etapa 124, en el interior del agujero 73 en el que está alojado el transistor 6 para aislar eléctricamente este último de su entorno y luego, durante una etapa 126, los pozos 80 y 82 son ahuecados en la resina aislante. Esta etapa 126 es por ejemplo realizada por un procedimiento de serigrafía o un procedimiento conocido con el término inglés de "dispensado". El ensamblaje obtenido a la salida de esta etapa 126 es el de la fig. 6D.The resin 74 of insulating dielectric material such as an epoxy resin, it is deposited, during a stage 124, inside the hole 73 in which the transistor 6 to electrically isolate the latter from its surroundings and then, during a stage 126, wells 80 and 82 are hollowed in the insulating resin This step 126 is for example performed by a screen printing procedure or a known procedure with the English term of "dispensed". The assembly obtained to the The output of this stage 126 is that of fig. 6D.
A continuación es depositado cobre, durante una etapa 128, en los pozos 80 y 82 así como sobre la cara superior de la lámina 25 de manera que forme los puntos de conexión 54, 56 y 58 con las pistas correspondientes grabadas sobre la cara superior de la lámina 25. El resultado obtenido a la salida de esta etapa está representado en la fig. 6E.Copper is then deposited during a stage 128, in wells 80 and 82 as well as on the upper face of sheet 25 so as to form connection points 54, 56 and 58 with the corresponding tracks recorded on the upper face of sheet 25. The result obtained at the end of this stage is depicted in fig. 6E.
Finalmente, durante una etapa 130, una nueva capa de la resina 74 es extendida sobre la cara superior de la lámina 25 de manera que aísle las pistas y puntos de conexión eléctricos y que asegure la planeidad de la cara superior del apilamiento destinada a recibir el ladrillo siguiente.Finally, during a stage 130, a new resin layer 74 is spread over the upper face of the sheet 25 so that it insulates the tracks and connection points electrical and ensure the flatness of the upper face of the stacking intended to receive the next brick.
A la salida de la etapa 130, las etapas 121 a 130 son reiteradas en el caso particular del apilamiento de un nuevo ladrillo intermedio sobre los ya apilados. Las etapas 121 a 130 son por tanto reiteradas tantas veces como componentes hay en la cadena 2, es decir aquí tres veces en total. Se observará sin embargo que durante la última iteración de las etapas 121 a 130, no es un ladrillo intermedio el que es apilado de manera similar a lo que ha sido descrito con respecto a las etapas 121 a 130 sino un ladrillo de extremidad.At the exit of stage 130, steps 121 to 130 are repeated in the particular case of stacking a new intermediate brick over the already stacked. Stages 121 to 130 are therefore repeated as many times as components are in chain 2, that is to say here three times in total. It will be observed without However, during the last iteration of steps 121 to 130, no it is an intermediate brick that is stacked in a similar way to what which has been described with respect to steps 121 to 130 but a limb brick.
Así, gracias a este procedimiento pueden ser fabricados ladrillos elementales y almacenados sin presagiar previamente su utilización.So, thanks to this procedure they can be manufactured elementary bricks and stored without presage previously its use.
Una célula de conmutación fabricada por ejemplo según el procedimiento de la fig. 5 presenta igualmente la ventaja de tener grupos de canales de circulación de fluido de refrigeración previstos por encima y por debajo de cada componente de potencia de manera que estos componentes de potencia son enfriados a la vez por su cara inferior y su cara superior. Gracias a ello, el enfriamiento de los componentes de potencia es más eficaz y las prestaciones eléctrica de la célula resultan mejoradas.A switching cell manufactured for example according to the procedure of fig. 5 also has the advantage of having groups of cooling fluid circulation channels provided above and below each power component of so that these power components are cooled at the same time by its lower face and its upper face. Thanks to that, the cooling of the power components is more efficient and the The electrical performance of the cell is improved.
La célula 20 sido descrita aquí en el caso particular en que las conexiones intermedias 7 y 8 no son accesibles a partir del exterior de sustrato 22. Sin embargo, en una variante, de manera similar a lo que se ha descrito para la conexión a la rejilla del transistor, para cada conexión intermedia, una lengüeta que sobresale sobre la cara trasera del sustrato 22 es conectada a esta conexión intermedia. Tal variante es particularmente ventajosa cuando la célula comprende un número par de transistores en serie y cuando está lengüeta suplementaria está conectada a la conexión intermedia situada en el centro de la cadena de manera que forme un punto medio. Tal célula de conmutación forma entonces por sí sola un brazo de un ondulador.Cell 20 been described here in the case. particular in that intermediate connections 7 and 8 are not accessible from the outside of substrate 22. However, in a variant, similar to what has been described for connection to the transistor grid, for each intermediate connection, a tab protruding on the rear face of the substrate 22 is connected to This intermediate connection. Such a variant is particularly advantageous. when the cell comprises an even number of series transistors and when this supplementary tab is connected to the connection intermediate located in the center of the chain so that it forms a middle point. Such a switching cell then forms by itself. An arm of an inverter.
La célula 20 ha sido descrita aquí en el caso particular en que los componentes de potencia están formados por diodos y transistores. Sin embargo, en una variante, estos componentes pueden ser reemplazados por los componentes apropiados para conmutar corrientes o tensiones tales como por ejemplo tiristores.Cell 20 has been described here in the case. particular in that the power components are formed by diodes and transistors. However, in a variant, these components can be replaced by the appropriate components to switch currents or voltages such as for example thyristors
Claims (16)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR0306748 | 2003-06-04 | ||
| FR0306748A FR2855912B1 (en) | 2003-06-04 | 2003-06-04 | POWER SWITCHING CELL, AND METHOD OF MANUFACTURING THE CELL |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ES2325921T3 true ES2325921T3 (en) | 2009-09-24 |
Family
ID=33155654
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| ES04300311T Expired - Lifetime ES2325921T3 (en) | 2003-06-04 | 2004-06-02 | POWER SWITCHING CELL, AND CELL MANUFACTURING PROCEDURE. |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6995409B2 (en) |
| EP (1) | EP1484797B1 (en) |
| AT (1) | ATE429034T1 (en) |
| DE (1) | DE602004020541D1 (en) |
| ES (1) | ES2325921T3 (en) |
| FR (1) | FR2855912B1 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7298034B2 (en) * | 2004-06-28 | 2007-11-20 | Semiconductor Components Industries, L.L.C. | Multi-chip semiconductor connector assemblies |
| US7202106B2 (en) | 2004-06-28 | 2007-04-10 | Semiconductor Components Industries, L.L.C. | Multi-chip semiconductor connector and method |
| DK1815514T3 (en) * | 2004-11-24 | 2008-08-25 | Danfoss Silicon Power Gmbh | A flow distribution module and a stack flow distribution module |
| CN101529693B (en) * | 2006-08-04 | 2013-10-30 | 净流有限合伙企业 | Axial air gap machine having stator and rotor discs formed of multiple detachable segments |
| KR100807980B1 (en) | 2006-11-27 | 2008-02-28 | 동부일렉트로닉스 주식회사 | Semiconductor device and the fabrication method thereof |
| US7773381B2 (en) | 2007-09-26 | 2010-08-10 | Rohm Co., Ltd. | Semiconductor device |
| CN112908943A (en) * | 2021-01-12 | 2021-06-04 | 华为技术有限公司 | Embedded packaging structure, preparation method thereof and terminal equipment |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4421319A1 (en) * | 1994-06-17 | 1995-12-21 | Abb Management Ag | Low-inductance power semiconductor module |
| US6060795A (en) * | 1998-03-18 | 2000-05-09 | Intersil Corporation | Semiconductor power pack |
| EP2234154B1 (en) * | 2000-04-19 | 2016-03-30 | Denso Corporation | Coolant cooled type semiconductor device |
| JP3894413B2 (en) * | 2000-06-08 | 2007-03-22 | 三菱電機株式会社 | AC generator for vehicles |
| JP2002026251A (en) * | 2000-07-11 | 2002-01-25 | Toshiba Corp | Semiconductor device |
| EP1318547B1 (en) * | 2001-12-06 | 2013-04-17 | ABB Research Ltd. | Power semiconductor module |
-
2003
- 2003-06-04 FR FR0306748A patent/FR2855912B1/en not_active Expired - Fee Related
-
2004
- 2004-06-01 US US10/858,293 patent/US6995409B2/en not_active Expired - Lifetime
- 2004-06-02 AT AT04300311T patent/ATE429034T1/en active
- 2004-06-02 EP EP04300311A patent/EP1484797B1/en not_active Expired - Lifetime
- 2004-06-02 ES ES04300311T patent/ES2325921T3/en not_active Expired - Lifetime
- 2004-06-02 DE DE602004020541T patent/DE602004020541D1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP1484797B1 (en) | 2009-04-15 |
| EP1484797A1 (en) | 2004-12-08 |
| FR2855912B1 (en) | 2006-04-14 |
| US6995409B2 (en) | 2006-02-07 |
| DE602004020541D1 (en) | 2009-05-28 |
| FR2855912A1 (en) | 2004-12-10 |
| US20050017264A1 (en) | 2005-01-27 |
| ATE429034T1 (en) | 2009-05-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5841500B2 (en) | Stacked half-bridge power module | |
| US9106124B2 (en) | Low-inductance power semiconductor assembly | |
| US5705848A (en) | Power semiconductor module having a plurality of submodules | |
| CN113013126A (en) | Half-bridge module of a traction inverter of a power electronics system of a vehicle | |
| US10867980B2 (en) | Semiconductor equipment | |
| JP7187992B2 (en) | Semiconductor modules and vehicles | |
| US9627356B2 (en) | Semiconductor module, semiconductor module arrangement and method for operating a semiconductor module | |
| US20090086427A1 (en) | Semiconductor device | |
| JP5831401B2 (en) | Semiconductor device | |
| ES2270928T3 (en) | LOW INDUCTANCE CIRCUIT PROVISION. | |
| JP6864713B2 (en) | Power module structure | |
| JPWO2016084622A1 (en) | Semiconductor device | |
| US10306814B2 (en) | Heat dissipation in power electronic assemblies | |
| JP6583072B2 (en) | Semiconductor module | |
| ES2325921T3 (en) | POWER SWITCHING CELL, AND CELL MANUFACTURING PROCEDURE. | |
| CN114551259A (en) | Method for producing a half bridge, power module for an inverter, and inverter | |
| ES2898791T3 (en) | power module | |
| ES2359548T3 (en) | ELECTRONIC POWER MODULE AND POWER COMPONENT INTENDED TO EQUIP SUCH MODULE. | |
| US11538725B2 (en) | Semiconductor module arrangement | |
| CN116582017A (en) | Switching module for an inverter, inverter comprising a plurality of such switching modules, and vehicle comprising an inverter | |
| US11410907B2 (en) | Semiconductor module | |
| JP2014192976A (en) | Semiconductor device | |
| US20240186217A1 (en) | Power module | |
| ES2774527T3 (en) | Electrical switching apparatus with an improved electrical interconnection device | |
| US20230238314A1 (en) | Printed Circuit Board, Power Semiconductor Module Arrangement Comprising a Printed Circuit Board, and Method for Assembling the Same |