ES2291057A1 - Measurement system with high time resolution and auto calibration is associated to temporary tag to asynchronous event by delay line, which provides programmable logic device, where exact moment of photon to hit detection system is measured - Google Patents

Abstract

The measurement system is associated to a temporary tag to an asynchronous event by delay line, which provides a programmable logic device of low cost. The exact moment, where a photon hits the detection system and detects equally coincident photons is measure by a positron emission tomography.

Description

High resolution time measurement system and self-calibration based on programmable logic device.

Technical sector

The technical sector in which the present invention is that of emission tomography of positrons, and other similar medical imaging systems, and in particular circuitry used in instant determination precisely in which a photon impacts the detection system.

State of the art

Positron emission tomography (PET) is based on the detection and identification of lightning pairs Gamma or high energy photons. This pair of photons, whose energy is 511KeV, it is the result of the annihilation of a positron by collision with an electron and propagate in directions practically opposite (180º), reaching the devices detectors practically in temporary coincidence.

For this purpose it is essential to device and mechanism that allows obtaining a temporary label for each photon, so that the temporal coincidence between photon couple resolves by comparing their temporary tags. Two photons are considered in temporary coincidence if the difference between its temporary tags is less than a certain value called match window.

Each pair of physically faced detectors constitutes a response line, and the activity seen in each response line, represented as the number of decays per unit of time, equivalent to the integral of the radioactivity within the volume defined by the mentioned response line. TO from the integral or projection of the activity it is possible to tomographic reconstruction of the activity at each point of the volume by means of algorithmic methods widely described in The scientific literature. In positron emission tomography the quality of the reconstructed image from the projections indicated above depends largely on the resolution and accuracy of the temporary tag associated with each individual photon detected.

In the current state of the art in tomography by positron emission, the time stamp is required associated with each photon have a resolution of less than 5 nano (n) seconds (s) if the reconstruction system Tomographic does not consider corrections for flight time (TOF), and less than 200 peak (p) seconds (s) if the mentioned correction.

In general, there are four alternative techniques for extracting the high-resolution time tag: the time-discrete converter (TDC), the Vernier delay line (VDL), the delay-locked loop (DLL) and oscillatory ring scanning . The present invention proposes a variant of the Venier delay line whose structure adapts to the physical and architectural characteristics of the granularity programmable logic devices
fine.

A common limitation of the devices of generation of existing brands, which employ one of the four cited techniques, is the need for a dedicated mixed electronics exclusively to the generation of temporary brands. This electronics can manifest itself well in the form of a circuit integrated specific purpose (ASIC) provided by a third party manufacturer, either as a set of discrete elements welded in the printed circuit, or as a mixed logic block inserted into an on-chip ASIC system more complex. Except for the last solution, the generation of the timestamp implies greater consumption of area within the printed circuit and, in any case, a higher system cost final.

In (Mota, Christiansen et al. 2000) it is described an ASIC used in particle physics experiments, which combines a passive delay line with a loop hooked on delay (DLL) to provide a high timestamp Resolution and automatic calibration.

In (Rieven 2003) and (Gu and Khieu 2003) it details the operation and problems of DLL circuits and VDL, and the typical structure of a delay line is shown Vernier. According to the procedure shown, a signal crosses the delay line that has N stages, and in each one of them suffers a certain delay \ tau_ {n}. In this way get as many delayed versions of the input signal as wish. In general, the system may include an encoder programmable, to select each of the stages, so that Each delay can be calibrated separately.

In (Kalisz, Szplet et al . 1997) the realization of a Vernier delay line on a programmable logic device (FPGA) is proposed, which requires careful programming of the device. The use of such devices is justified as a way to substantially reduce development costs and an FPGA based on amorphous antifuse structures, an architecture with little commercial success, is selected as the optimal implementation technology. However, the conclusion of this work is that, due to the problem of fine time correction that results in multiple design iterations and, since this technology allows a single programming, the resulting design process is not as economical as initially The author claims.

In (Fries 2003) a variation is proposed to the Vernier delay line, in which instead of delaying the signal of the event, the clock signal is delayed. This is done using a module, available within some logical devices Most recent programmable, which allows you to enter a offset Controlled in the clock signal. In this way four are derived clock signals offset 90º to each other, which results in a temporal resolution that is a quarter of the master clock period employee. This solution is characterized by its simplicity of implementation, but imposes an important restriction on the working frequency of the device to achieve resolution desired, which results in more expensive programmable devices.

The communication summary (Wu, Shi et al . 2003) proposes the use of the existing haul line in modern FPGAs for the realization of a Vernier delay line. This carry line is originally intended for the propagation of the carry signal in arithmetic operations within the FPGA, and is characterized by its regularity and low delay, providing a predefined and homogeneous route within the FPGA, which can be assimilated to a passive line RC (resistance-capacitor). Due to its characteristics, this solution provides a resolution of this delay line much lower than the nanosecond at the cost of an important area consumption within the FPGA, while the long haul lines needed to implement this method include multiple non-linearities. of the parasitic capacities that load the line and the transitions between columns of the device, which affect the performance of the circuit.

The properties of the delay line depend largely of the supply voltage, temperature and underlying technological process. For this reason the variability of these factors influence the measure, and require a process of calibrated to make the aforementioned measure independent of External factors mentioned. In a delay line implemented in an ASIC the variability is solved by means of a control in closed loop that adjusts the delay of each stage until a predefined delay, as shown in (Roger and Grigorievich 2002) and in (Rieven 2003). These analog solutions they are not possible in an FPGA and should be considered a method Alternative calibration using exclusively digital methods. A person skilled in the art does not miss that said calibration must be performed continuously in order to correct the temporal variations of these factors.

Consequently, methods and devices currently existing to introduce high delays precision in an individual signal based on logical devices programmable do not provide the necessary benefits, in what resolution and flexibility refers to the generation of Temporary labels on positron emission tomography.

Explanation of the invention.

The present invention provides a method and apparatus for introducing delay in a signal, individual and not periodic, whose benefits are adapted to the application before mentioned, and for which a logical device is used Programmable (FPGA) fine granularity.

Programmable logic devices they constitute an interesting alternative to solutions based on specific integrated circuits (ASIC) or solutions based on discrete external components, not only because of their reduced cost but for the reduction in area that this implies, as well as the possibility of integration of the delay line into a digital design more complex.

The temporal resolution of the proposed invention it is a function of the technological process of the FPGA used, as well as of the temperature and supply voltage of the device. In ambient conditions the resolution of the proposed invention is of order of 1 ns.

The present invention involves a solution of low cost that makes use of physical characteristics and architecture of the latest programmable logic devices generation to achieve a balance between resolution and area, which integrates self-calibration, and that can be described in a language of fully synthesizable high level, which favors migration towards new FPGA devices.

The object of the present invention is a system Instant time measurement with high resolution and self-calibration based on programmable logic device (FPGA), which determines the instantly an external non-periodic event takes place that It comprises the following subsystems:

to.

a external event detection subsystem asynchronous to the signal master clock,

b.

a high resolution time measurement subsystem comprising an analog delay line that provides a measure of time between two events, the external event and the clock signal internal, and in which the analog delay line is regenerative and its configurable functionality,

C.

a calibration subsystem, which estimates the delay introduced by each delay circuit stage by means of a calibration pulse of known duration and an equivalent analog delay line to the one used for the measurement of time,

d.

a Subsystem for generating the temporary tag associated with the event asynchronous

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In said time measurement system, the subsystem for the detection of asynchronous events monitors the status of the line associated with the event, with a periodicity determined by the master clock signal, and identifies the occurrence of an event on the line associated with the external asynchronous signal as a change in the state of the line, detecting either a flank or a change in the level of said signal, and generating a pulse of duration a clock cycle that indicates the other subsystems that in the cycle From the clock before the mentioned pulse an event occurred for which you want to generate a temporary label.

In the aforementioned time measurement system, the high resolution and calibration time measurement subsystems include a Vernier analog delay line which comprises

to.

AND delay stages, where E is a function of the master clock period and of the delay introduced by each stage and its value is such that guarantees that the total delay introduced exceeds the period T of the master clock at the working temperature where the delay per stage is minimal, each of which is performed on a programmable logical device configuration cell e introduces an incremental delay over the analog signal of input, in which this delay introduced on the signal is of Two types: discreet and distributed; the first has its origin in the configuration cell configuration; while the second they have their origin in the line of physical interconnection between cells of  consecutive configuration on the analog delay line, where the physical interconnection path that the signal follows in its Propagation along the analog delay line is selected so that the delay introduced by the elements of interconnection between consecutive configuration cells be balanced,

b.

AND records, one for each delay stage, that sample the status of the analog delay line at regular intervals triggered by the flank of the master clock, and the one that capture is enabled by a control signal activated by the subsystem to which the analog delay line belongs,

C.

three inputs: the clock, the enable signal and the signal on which the delay is entered; and E outputs, one for each record of sampling.

For the realization of each of the delay stages of said analog delay line, an FPGA configuration cell is used . Within the said configuration cell, the configuration table (LUT) is used, usually a static RAM, as a delay element, which gives the delay element the regeneration properties of the voltage, restoring the line voltage analog delay to the values corresponding to the logical "1" and "0", and configurability of the delay element.

Each configuration table of each configuration cell belonging to the analog delay line is configured so that it performs one of the following logical functions: buffer, in which the logic value at the output is equal to the input, logic function AND, function OR logic or two-input multiplexer. In a preferred embodiment, said configuration table is configured as a buffer having three inputs: a clock signal, an enable or capture signal and an input for the signal that propagates through the analog delay line; and two outputs: one with the analog signal that propagates through the analog delay line on which an additional delay has been introduced by means of the programmable table, and a signal that provides the state of the line at the time of capture, marked by the flank of the clock signal. Furthermore, in a preferred embodiment, the consecutive configuration cells in the analog delay line are physically placed in consecutive positions of the programmable logic device, either by rows or by columns; and because the relative interconnection between consecutive cells makes use of the same switching channels, so that the delay between consecutive cells is equivalent for all pairs of consecutive configuration cells.

The high resolution time subsystem of the said high resolution time measurement system comprises the following elements:

to.

a analog delay line, whose input connects to a signal external, associated with the asynchronous event whose instant of occurrence you want to register, and whose enable signal is connected with the pulse detection signal generated by the subsystem to asynchronous event detection,

b.

a bus that combines the reading of the different sampling records, so that the most significant n bits have a certain value logical when an event is detected and the remaining records on complementary logical value, where n indicates the number of stages that the input signal associated with the event goes through its propagation along the line between the moment the event occurs and the moment at which the state of the line is sampled, determined the rising or falling edge of the clock signal, and its value is always less than or equal to the number of delay stages E,

C.

a decoder that transforms the bus value, resulting from grouping the values of the E sampling records, in a new code that facilitate its interpretation by the remaining subsystems of the time measurement system.

It should be noted that a preferred embodiment the decoder of said subsystem for the measurement of time with high resolution transforms the reading of the E registers into an unsigned integer, represented in complement to two, indicating the number of elements crossing the line of analog delay between the moment at which the input to the analog delay line changes level and the moment at which the state of the line is sampled.

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On the other hand, the calibration subsystem of the aforementioned system for high resolution time measurement comprises the following elements:

to.

a record type flip-flop, whose input is the pulse generated by the synchronous counter,

b.

a analog delay line, which is physically parallel to the main analog delay line and using the closest possible row or column, according to the technological restrictions imposed by the FPGA, and whose signal of analog delay line enablement is the output of the flip-flop log,

C.

a synchronous counter with the master clock that periodically generates a pulse of constant duration that is taken as an input signal to the analog delay line,

d.

a autoregressive filter that averages the readings made by the analog calibration delay line, and whose value is update with each pulse generated by the counter synchronous,

and.

a record for storage of the last calibration value, whose value is updated with the result provided by the filter autoregressive and which reflects the number of delay stages that crosses a pulse of known duration for a period of master clock, and from which therefore the delay is obtained entered for each of the delay cells.

The results of the time measurement and calibration subsystem are the inputs of the temporary label generation subsystem associated with the external event, which comprises:

to.

a synchronous cyclic counter with the master clock, whose value is Increase by one with each clock cycle and return to zero when overflow occurs,

b.

a calculation subsystem that, upon detection of an asynchronous event abroad, combine the information provided by the aforementioned synchronous counter with the value stored in the register of Calibration subsystem storage and with reading provided by the analog delay line associated with the signal external

The sequence of operations required to obtain the temporary label in the temporary label generation subsystem from the data provided by the time measurement subsystem and the calibration subsystem is based on the method followed in the development of the line of main analog and calibration delay, so that the event is considered to take place the instant of time resulting from multiplying the value of the counter of the temporary label generation subsystem by the clock period and discounting from this value the result of multiplying the reading of the main analog delay line, at the decoder output of the time measurement subsystem, for the clock period normalized by the value stored in the calibration register. In this way the calculation subsystem belonging to the temporary label generation subsystem
understands

to.

a multiplier, whose inputs are a constant value that expresses the known duration of the calibration pulse and the value provided by the time resolution subsystem with high resolution at decoder output,

b.

a divisor, which divides the result at the exit of the first multiplier by the value stored in the subsystem register of calibration that stores the last calibration value,

C.

a multiplier, whose inputs are a constant value that expresses the duration of the clock cycle and the value provided by the counter  synchronous tag generation subsystem temporary,

d.

a subtractor, which discounts the result of the value divisor to the output of the second multiplier, which scales the synchronous counter Through the clock period.

An alternative embodiment of the time resolution system with high possible resolution is one that combines the time resolution subsystems with high resolution and calibration , so that they share in time the use of a single physical delay line common to both subsystems .

In this alternative embodiment of the time measurement system, the first delay stage of the analog delay line has 5 inputs: a clock signal, an enable signal and three inputs acting on the configuration table, which is configured as a multiplexer with two inputs, the signal from outside and the calibration pulse, plus a third signal selects between one or the other, while the configuration tables of the remaining configuration cells belonging to the analog delay line have a single input , so that the output is equal to the input plus a certain time delay; in this way the analog delay line takes pulses from outside or the calibration subsystem as input, and both subsystems share a single physical delay line over time.

Regardless of the chosen embodiment for the development of the time measurement system with high resolution, a loop circuit is engaged in phase or delay to reduce the variability (jitter) of the signal of the system master clock from outside.

The aforementioned time measurement system set forth in this description can be used as a building block of one of the following medical imaging systems : positron emission tomography scanner (PET), nuclear magnetic resonance imaging (NMR), computed tomography -X (CT), individual photon emission tomography (SPECT) and optical tomography.

Description of the drawings

Fig. 1: Vernier delay line generic

Fig. 2: Time diagram for the line of Vernier

Fig. 3: Example of cell configuration programmable logic device base

Fig. 4: Delay line implemented on a programmable logic device

Fig. 5: Placing and challenging the delay line Vernier in the programmable logic device

Fig. 6: Example of circuit for generating the validation signal of the data present in the records of Vernier delay line capture.

Fig 7: Embodiment of the invention with two delay lines

Fig 8: Embodiment of the invention with a single delay line

DISCLOSURE OF AN EMBODIMENT OF THE INVENTION

A subject specialist will appreciate that The following description of the present invention has character illustrative and that the invention is not limited to the example here exposed.

An example of a line is shown in Fig. 1 Typical vernier with several delay elements. This example of Vernier line (Fig. 1) shows a chain in which three delay elements (111), (112), (113) delay a signal from entrance (12) from outside, and three other elements of delay (131), (132), (133) delay the stop signal (14). The different delayed versions (151), (152), (153) of the signal input are the input of a storage item (171), (172), (173), p. ex. a flip-flop (FF), and the flank of the different delayed stop signals trigger the capture of the value present in the delay line. This figure shows assumes that the Ti delays introduced by the delay elements (111-113), (131-133) are estimates or determined by an additional calibration circuit no contemplated in this figure.

In Fig. 2 a possible diagram of times for a typical Vernier line (Fig. 1). Imagine that in the instant t_ {0} (21) the input signal (12) is activated, indicating the detection of a certain external event, and that the capture signal of the state of the delay line occurs instantly t_ {0} + \ Deltat (22). In the example shown, it is considered that no any delay is introduced in the capture line, so that the different delays (131), (132), (133) are negligible, and that the input signal is delayed in time so that the storage logs are fed by delayed copies (151), (152), (153) of the original signal (12). In this example the relationship between the time interval \ Deltat elapsed between the event and the capture is such that the input signal is only it has propagated until it reaches the first record (171), but not remaining. In the capture records (161), (162), (162), find the state of the line coded (23) at the instant of the capture, which takes place with the rising edge of the signal from clock, and in which those records that were high are high reached by the input pulse in its propagation along the delay line. It is clear that the higher the number of records at a high level, the greater the time elapsed between the moment in which the event occurs and the moment of capture. A decoder circuit (18) transforms this register code to high level and low level records, in another one that is higher interest in later stages of processing (19), being a possible solution the transformation into an integer if sign whose value It is equal to the number of high level records.

An example of embodiment of the typical Vernier line apparatus (Fig 1) on a programmable logic device, and a method and apparatus will be described to obtain the delays introduced in the device.

The completion of the delay line is achieved through special programming of the different components of the programmable logic device. For this it is necessary to specify the configuration of the elementary cells and the interconnection between cells, so that the circuit is functionally equivalent to described in the typical Vernier line (Fig. 1).

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An example configuration for the elementary cell of the FPGA is shown in Fig. 3. In this example, the basic cell consists of two RAM tables of four entries each and two FF records. As shown in this figure, one of the RAM (330) / FF (331) pairs is programmed such that the input signal to the elementary cell (310) crosses the memory table (330) and gives rise to two copies of the input signal (353), (354). The cell has two output lines (320), (321). The first of the mentioned outputs (320) is a delayed copy of the input signal (310), in which the delay is introduced by the connection, the memory table and the configuration multiplexers, and has the value ta * CLB = ta * 0 (350) + ta * 1 (351) + ta * 2 (350) + ta * 3 (350). The second of the copies produced (354) feeds the entry of the capture register (331). The master clock signal (313) is connected to the clock input of the FF acting as a capture signal, and this is validated with an enable signal, enable (312). If the memory table is configured in such a way that it performs the function of a regenerating buffer, with D = A4, then the elementary cell (Fig. 3) (41) (42) is functionally equivalent to a buffer (111) that introduces a delay on an input signal (310) (410) and whose result results in two outputs obtained to capture the output signal of the buffer by registration (321) (416) and another that is a delayed copy (320) (415) of the input signal.

The configuration of the memory table as a buffer has a double function, on the one hand it introduces a certain delay ta * 1 (351), which is independent of the logical function that implements the aforementioned table, and on the other regenerates the voltage of the delay line preventing lines Long delay with multiple configurable blocks occur a voltage drop, consequence of the capacities and resistances parasites along it; this fact benefits of the linearity of the measurement system. Any delay introduced on the signal is a function of the technological process and of the local temperature of the electronic circuit, so that it results necessary a device and calibration method that provides the value of the aforementioned delay and allow to follow its fluctuations Temporary

It should be noted that the tools Commercial for design with FPGA are designed for realization of digital systems. For this reason the realization of  analog solutions, such as the delay line proposed in this invention, require an unconventional design methodology which does not correspond to the working hypothesis with which develop these tools, which is why the flow of resulting design conflicts with the algorithms of analysis, optimization and synthesis present in the tools commercial, making it difficult to perform a configuration of these characteristics and making a deep knowledge necessary and detailed of the design tool itself.

Fig. 4 shows the functionality of the stage 1 and 2 cell, configured as shown in the Fig. 3. By simplification, \ * 5 = is defined ta * 0 (350) + ta * 1 (351) + ta * 2 (325), The specialist in the field may observe the functional equivalence between the delay stage Classic Vernier shown in Fig. 1 and that of the elementary cell of the FPGA of Fig. 4. The Vernier delay line is constructed as a concatenation of elementary cells (41), (42) configured such and as described in Fig. 3. The input signal of stage 2 (420) is the output of stage 1 (415) plus a certain delay ta * i + 1, PROP} (402) that depends on the interconnection path between both elementary cells. By having all the cells identical elementary configuration can be assumed that, saving the variability due to the manufacturing technological process, all stages introduce the same delay \ tau * = ta * PROP (402) + ta * 5 + ta * 3 (353) - * * 4 (354).

An outline of the positioning within the FPGA of the first three cells elementals (40), (41), (42) of the Vernier delay line. The cited elementary cells are set up as described in the Fig. 3 and has the functionality described by Fig. 4. As advanced in the description of the invention, the present invention exploits the architectural properties of the FPGA, specifically the interconnected between consecutive cells the regularity explodes of the different switching matrices (520), (521), (522) within of the device, which allows the connection path between each pair consecutive cells always be the same and therefore the delay introduced by the connection between cells is the most homogeneous possible so that for all stages \ tau * _ {j, PROP} \ approx \ tau * _ {i, PROP}, except for the first, that connects the line with the input pad or with the calibration circuit

From the functional point of view it does not affect the fact that the connection path of the first stage (400), which connect the input pad (50) with the first cell (40), be different from the others and therefore the delay of ta * 0, PROP} is slightly different from ta * PROP}, since the difference between both values a constant bias is considered that affects all equally, as long as the connection path between the input pad and the first elementary cell is the same for all the delay lines present in the FPGA.

Preferably the first delay cell is it will physically place as close as possible to the input pad (50). It should be noted that the positioning and routing algorithms present in commercial design tools for rare FPGA once they will ensure regularity in the positioning of the blocks and signal routing, so it is necessary to go to advanced positioning mechanisms that usually provide cited tools.

The regularity described both in positioning as interconnected significantly reduces non-linearities of the measuring device and allows the claim that the delays of all cells are equivalent, of value \ tau * = \ tau * _PROP + \ tau * 0 + ta * 1 + ta * 2 + ta * 3 - ta * 4, and playable by another delay line that has the same scheme of positioning and connection. This fact allows the realization of a calibration circuit that measures the number of stages that are they cross in a known time, and from there the delay of each cell of the calibration delay line, which is equivalent to that of the main delay line.

In Fig. 5 (40), (41), (42), a 3-stage delay line in which the connection is highlighted through which the input pulse is propagated, as you can see, the switching blocks (520), (521), (522) are configured so that the connection path between stages (401), (402) is the Same for all cells. The first stage (40) connects (400) the line to the outside world through pad (50), or to a circuit calibration that provides the necessary pulses for the obtaining the delay introduced in each stage. The number of stages E in the delay line necessary for the measurement of time is a function of the period of the master clock and the delay introduced by each stage. During the design phase it select a number of stages E that ensures that the delay total entered either, at the working temperature where the delay per stage is minimum, greater than the period T of the master clock. This fact creates a dependency between the number of necessary stages and the underlying technology that does not affect the spirit of the invention.

A possible embodiment is shown in Fig. 6 of the event detection circuit. The aforementioned circuit determines if an event occurred within the last capture cycle. He specialist in the field can determine that said circuit will generate a pulse (60) if there is a change in the state of the input signal (12) in two consecutive capture periods. He said pulse validates the value at the output of the decoder of the Vernier line (19). Preferably the capture device most recent (601) is as close as possible to the pad of entry, and preferably the existing record is selected in many FPGAs in the same pad (50).

The said decoder (18) provides a N value related to the instant within the capture cycle, preferably a cycle of the master clock of period T, in which The event occurs. The event occurs \ Deltat = \ tau \ cdotN ns (21) before the capture edge (22), where ta, which reflects the delay introduced by each stage of delay, is unknown and variable over time and its value is Estimate through the calibration process. The value of N will be always less than the total number E of delay stages in the delay line, where E is a function of the master clock period and of the delay introduced by each stage.

Calibration is done by injection periodic in the delay line of a signal of known duration and generated internally. The present invention proposes two alternatives,

the first, whose scheme is summarized in Fig. 7, employs a delay line (72) dedicated exclusively to the process of calibration of the main line (71), and that physically stands as close as possible to the main delay line, with the so that the thermal and technological conditions are the most similar possible. Both delay lines obey the same positioning and interconnection scheme, so that the delays introduced by the various elements in a case and the other are as similar as possible. In this embodiment the signal external (12) and the associated control control logic (74) is independent of the calibration pulses and their control logic associated (75).

The calibration logic combines the result obtained by injecting several calibration pulse (76), and stores the resulting value in the calibration record (77), the value stored in this register an estimate of the number of stages of the line that crosses a pulse of known duration during a clock period. At each detection of a new event (60), the temporary label (79) is obtained by combining the reading of the main status line (71) with the calibration status (77).

The second alternative, whose scheme is summarized in Fig. 8, the independence of the delay ta * 1 explodes (351) introduced by the RAM table (330) of the logical function that It implements. In this alternative configuration the RAM table of the first cell of line 40 is configured as a multiplexer (82), which can take as input two different signals, the signal delayed from outside (12) or other internally generated for calibration (75) depending on the value of a third signal of selection (84) generated by the control logic (81), while the remaining cells maintain the configuration described with anteriority. In this second embodiment the first table of the Vernier line develops a double function, on the one hand as multiplexer and on the other as a delay element. Through this multiplexing mechanism can be periodically injected the calibration signal in the delay line without any existing any difference between delays in normal mode and mode calibration. As a result of the temporal multiplexing of both functions, it is not possible to detect those events that have  place during a calibration period.

The control logic (84) will manage the value present in the delay line (86), updating the status of the calibration record (77) in the case of a pulse of calibrated, or by combining (89) the delay line reading with the calibration record in the pulses that have their origin in an external event, for which the label is obtained temporary (79) associated with the event.

The calibration pulse has a duration T equal to the duration of the capture cycle. As a consequence of the propagation time between the generation and the entry of the Vernier calibration delay line as well as the setting, setup time of the capture registers, the effective duration of the calibration pulse is T '= T - T * , where T * is estimated from the specification sheet of the device manufacturer. The calibration circuit obtains the number of stages that a pulse of known duration T passes through. '' The calibration circuit may include an averaging circuit that estimates n '' as the average of several calibration measurements. The value n '' is called the state of the calibration record (77), and its value is variable over time, a possible realization of this estimate (76) is by means of the average of the calibration result in the last M pulse of calibration.

one

The realization of the averaging as it is shown in the previous expression is expensive in hardware resources, therefore an alternative embodiment is the realization of a first-order autoregressive filtering for which a memory factor p, so that after each new pulse of calibrated the memory factor weights the reading in the line of Calibration and the current status of the calibration log:

2

The value of p determines the weight given to previous measures versus new ones; to simplify the resulting hardware is beneficial to take p as a rational of the form k / 2q with arbitrary k and q.

Combining expressions

3

The temporary tag generator circuit (78) includes the logic necessary to estimate \ Deltat from the measure provided by the decoder (19) and the one obtained at from the calibration measurements. The \ Deltat measure extends the resolution of the temporary label beyond the resolution provided by the master clock. It should be noted that \ Deltat it is an estimate of the time that elapses between the event and the next capture flank, determined by the clock flank teacher. Time is usually of more interest elapsed between the last clock flank and the event, and whose values

4

The generated circuit of the temporary tag includes an external counter to the synchronous delay line with the master clock, whose resolution is that of the clock, which provides greater custom dynamic range and whose value is stored in the C record.

Upon detection of a particular event, the associated temporary tag is obtained from the counter synchronous and decoder reading combined with the calibration information (79). So it is estimated that the event E takes place instantly

5

Expression that can be simplified by

6

In the case of emission tomography of positrons, two different events are said to coincide if the difference between your tags is less than a certain threshold called a match window

7

When performing the calculation by arithmetic digital, it is usual to normalize with respect to the clock period, in which case T * will be simplified against T. Thus it is said that two events are coincident if it is fulfilled that:

8

The aforementioned temporary tag is sent to a external circuit and which is not the subject of the present invention, and that will determine if any couple of events are in coincidence temporary or not.

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Documents cited

Fries , MD ( 2003 ). System and Method for Ascribing times to events in a medical imaging system. US Patent Application Publication . US US 2003/0047686 A1.

Gu , L. and CQ Khieu ( 2003 ). Variably controlled delay line for read data capture timing window. US2003226053. H04L5 / 00.

Kalisz , J., R. Szplet, et al . ( 1997 ). "Field-programmable-gate-array-based time-to-digital converter with 200-ps resolution". Instrumentation and Measurement, IEEE Transactions on 46 (1): 51-55.

Mota , M., J. Christiansen , et al . ( 2000 ). A flexible multi-channel high-resolution time-to-digital converter ASIC . Nuclear Science Symposium Conference Record, 2000 IEEE.

Rieven , SA ( 2003 ). Apparatus And Method For Introducing Signal Dalay. WO03083503. G01S3 / 00.

Roger , DA and AV Grigorievich ( 2002 ). Programmable self-calibrating Vernier and method. Russia.
WO02095943.

Wu , J., Z. Shi , et al . ( 2003 ). Firmware-only Implementation of Time-to-Digital (TDC) in Field-Programmable Gate Array (FPGA) . Nuclear Science Symposium.

Claims (17)

1. Time measurement system with high resolution and self-calibration based on programmable logic device (FPGA) comprising the following subsystems:

to.

a external event detection subsystem asynchronous to the signal master clock,

b.

a High resolution time measurement subsystem, which takes as input the value provided by the detection subsystem of external asynchronous events, which includes a delay line analog and that provides a measure of the time between two events, the external event and the internal clock signal, and in which The analog delay line is regenerative and its functionality configurable,

C.

a calibration subsystem, which takes a pulse as input stimulus internal periodic calibration and of known duration, for estimate the delay introduced by each stage of the circuit delay and consisting of an equivalent analog delay line to the one used for the measurement of time,

d.

a Temporary tag generation subsystem, powered by the time measurement subsystem and calibration subsystem, which provides a digital value related to the instant of occurrence of the asynchronous event.

2. Time measurement system according to claim 1 characterized in that the subsystem for the detection of asynchronous events monitors the state of the line associated with the event, with a periodicity determined by the master clock signal, and identifies the occurrence of an event in the line associated with the asynchronous external signal as a change in the state of the line by detecting either a flank or a change in the level of said signal, and generating a pulse of duration a clock cycle that indicates the other subsystems that in the clock cycle before the mentioned pulse an event occurred for which you want to generate a temporary label. 3. Time measurement system according to claim 2, characterized in that the high resolution and calibration time measurement subsystems include an analog delay line which comprises:

to.

AND delay stages, where E is a function of the master clock period and of the delay introduced by each stage and its value is such that guarantees that the total delay introduced exceeds the period T of the master clock at the working temperature where the delay per stage is minimal, each of which is performed on a programmable logical device configuration cell e introduces an incremental delay over the analog signal of input, in which this delay introduced on the signal is of Two types: discreet and distributed; the first has its origin in the configuration cell configuration; while the second they have their origin in the line of physical interconnection between cells of  consecutive configuration on the analog delay line, where the physical interconnection path that the signal follows in its Propagation along the analog delay line is selected so that the delay introduced by the elements of interconnection between consecutive configuration cells be balanced,

b.

AND records, one for each delay stage, that sample the status of the analog delay line at regular intervals triggered by the flank of the master clock, and the one that capture is enabled by a control signal activated by the subsystem to which the analog delay line belongs,

C.

three inputs: the clock, the enable signal and the signal on which the delay is entered; and E outputs, one for each record of sampling.

4. Time measurement system according to claims 3, characterized in that each of the E FPGA configuration cells belonging to the analog delay line uses the configuration table (LUT), usually a static RAM, as a delay element, which gives the delay element the voltage regeneration properties, restoring the analog delay line voltage to the values corresponding to the logical "1" and "0", and configurability of the delay element. 5. Time measurement system according to claims 4 characterized in that the configuration table of each configuration cell belonging to the analog delay line is configured so that it performs one of the following logical functions: buffer, in which the logical value at output is equal to the input, AND logic function, OR logic function or two-input multiplexer. 6. Time measurement system according to claims 5, characterized in that, in a preferred embodiment, said configuration table is configured as a buffer having three inputs: a clock signal, an enable or capture signal and an input for the signal that propagates through the analog delay line; and two outputs: one with the analog signal that propagates through the analog delay line on which an additional delay has been introduced by means of the programmable table, and a signal that provides the state of the line at the time of capture, marked by the flank of the clock signal. 7. Time measurement system according to claims 6, characterized in that, in a preferred embodiment, the consecutive configuration cells in the analog delay line are physically located in consecutive positions of the programmable logic device, either by rows or by columns; and because the relative interconnection between consecutive cells makes use of the same switching channels, so that the delay between consecutive cells is equivalent for all pairs of consecutive configuration cells. 8. Time measurement system according to claims 1 to 7, characterized in that the subsystem for measuring the time with high resolution comprises:

to.

a analog delay line, whose input connects to a signal external, associated with the asynchronous event whose instant of occurrence you want to register, and whose enable signal is connected with the pulse detection signal generated by the subsystem to asynchronous event detection,

b.

a bus that combines the reading of the different sampling records, so that the most significant n bits have a certain value logical when an event is detected and the remaining records on complementary logical value, which indicates the number of stages that the input signal associated with the event goes through its propagation to along the line between the moment the event occurs and the moment at which the state of the line is sampled, determined the  rising or falling edge of the clock signal, and its value is always less than or equal to the number of delay stages E,

C.

a decoder that transforms the bus value, resulting from grouping the values of the E sampling records, in a new code that facilitate its interpretation by the remaining subsystems of the time measurement system.

9. Time measurement system according to claims 1 to 8, characterized in that, in a preferred embodiment, the decoder of the subsystem for the measurement of time with high resolution transforms the reading of the E registers into an unsigned integer, represented in complement to two , which indicates the number of elements crossing the analog delay line between the moment at which the input to the analog delay line changes level and the moment at which the state of the line is sampled. 10. Time measurement system according to claims 1 to 9, characterized in that the calibration subsystem comprises the following elements:

to.

a record type flip-flop, whose input is the pulse generated by the synchronous counter,

b.

a analog delay line, which is physically parallel to the main analog delay line and using the closest possible row or column, according to the technological restrictions imposed by the FPGA, and whose signal of analog delay line enablement is the output of the flip-flop log,

C.

a synchronous counter with the master clock that periodically generates a pulse of constant duration that is taken as an input signal to the analog delay line,

d.

a autoregressive filter that averages the readings made by the analog calibration delay line, and whose value is update with each pulse generated by the counter synchronous,

and.

a record for storage of the last calibration value, whose value is updated with the result provided by the filter autoregressive and which reflects the number of delay stages that crosses a pulse of known duration for a period of master clock, and from which therefore the delay is obtained entered for each of the delay cells.

11. Time measurement system according to claims 1 to 10 characterized in that the temporary label generation subsystem comprises:

to.

a synchronous cyclic counter with the master clock, whose value is Increase by one with each clock cycle and return to zero when overflow occurs,

b.

a calculation subsystem that, upon detection of an asynchronous event abroad, combine the information provided by the aforementioned synchronous counter with the value stored in the register of Calibration subsystem storage and with reading provided by the analog delay line associated with the signal external

12. Time measurement system according to claims 1 to 11, characterized in that the subsystem for generating the temporary label is based on the method followed in the elaboration of the main analog delay and calibration line, so that it is considered that the event takes place the instant of time resulting from multiplying the value of the counter of the generation subsystem of the time tag by the clock period and discounting from this value the result of multiplying the reading of the main analog delay line, to the decoder output of the time measurement subsystem, for the clock period normalized by the value stored in the calibration register. 13. Time measurement system according to claims 1 to 12, characterized in that the calculation subsystem belonging to the temporary label generation subsystem comprises

to.

a multiplier, whose inputs are a constant value that expresses the known duration of the calibration pulse and the value provided by the time resolution subsystem with high resolution at decoder output,

b.

a divisor, which divides the result at the exit of the first multiplier by the value stored in the subsystem register of calibration that stores the last calibration value,

C.

a multiplier, whose inputs are a constant value that expresses the duration of the clock cycle and the value provided by the synchronous counter of the tag generation subsystem temporary,

d.

a subtractor, which discounts the result of the value divisor to the output of the second multiplier, which scales the synchronous counter Through the clock period.

14. Time measurement system according to claims 1 to 10, characterized in that in a possible alternative embodiment the time resolution subsystems are combined with high resolution and calibration, so that they share in time the use of a single line of physical delay common to both subsystems. 15. Time measurement system according to claims 1 to 10 and 14, characterized in that the first delay stage of the analog delay line has 5 inputs: a clock signal, an enable signal and three inputs acting on the table of configuration, which is configured as a multiplexer with two inputs, the signal from outside and the calibration pulse, plus a third signal selects between one or the other, while the configuration tables of the remaining configuration cells belonging to the line Analog delay have a single input, so that the output is equal to the input plus a certain time delay; in this way the analog delay line takes pulses from outside or the calibration subsystem as input, and both subsystems share a single physical delay line over time. 16. Time measurement system according to claims 1 to 15 characterized in that in a preferred embodiment a loop circuit is engaged in phase or delay to reduce the variability (jitter) of the master clock signal of the system from outside . 17. Use of the time measurement system according to claims 1 to 17 a building block of one of the following medical imaging systems: scanner for tomography Positron emission (PET), nuclear magnetic resonance imaging (NMR), X-ray computerized tomography (CT), emission of individual photon emission (SPECT) and tomography optics.