ES2128938A1 - Method for determining on which line of an intermediate high-speed memory in the memory architecture of a computer (associative two-way set cache) a particular piece of data is located - Google Patents

Method for determining on which line of an intermediate high-speed memory in the memory architecture of a computer (associative two-way set cache) a particular piece of data is located

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Publication number
ES2128938A1
ES2128938A1 ES09601212A ES9601212A ES2128938A1 ES 2128938 A1 ES2128938 A1 ES 2128938A1 ES 09601212 A ES09601212 A ES 09601212A ES 9601212 A ES9601212 A ES 9601212A ES 2128938 A1 ES2128938 A1 ES 2128938A1
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Spain
Prior art keywords
memory
associative
cache
computer
determining
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Granted
Application number
ES09601212A
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Spanish (es)
Other versions
ES2128938B1 (en
Inventor
Hormigo Antonio Juan
Guerrero Juan Jose Navarro
Korpel Tomas Lang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Universitat Politecnica de Catalunya UPC
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Universitat Politecnica de Catalunya UPC
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Application filed by Universitat Politecnica de Catalunya UPC filed Critical Universitat Politecnica de Catalunya UPC
Priority to ES9601212A priority Critical patent/ES2128938B1/en
Publication of ES2128938A1 publication Critical patent/ES2128938A1/en
Application granted granted Critical
Publication of ES2128938B1 publication Critical patent/ES2128938B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

Method for determining on which line of an intermediate high-speed memory in the memory architecture of a computer (associative two-way set cache) a particular piece of data is located. In present-day processors, which work with a high- frequency clock, the cache memory (intermediate, high- speed memory in the memory architecture of a computer) within the processor is a direct map. This is due to the fact that, although it has a higher failure rate than that of associative set memories, it has the best access time. The process pattern could consist of an associative two-way cache which makes it possible to recover the element sought before knowing whether it is present or absent, characterised in that, faced with the presence of a memory address for the cache, the element sought is recovered by means of the use of information stored in a new memory structure.
ES9601212A 1996-07-01 1996-07-01 PROCEDURE TO DETERMINE IN WHICH ROUTE OF A RAPID INTERMEDIATE MEMORY IN THE MEMORY HIERARCHY OF A COMPUTER MEMORY (CACHE) ASSOCIATIVE BY SET OF TWO WAYS IS FOUND A SPECIFIC DATA. Expired - Fee Related ES2128938B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
ES9601212A ES2128938B1 (en) 1996-07-01 1996-07-01 PROCEDURE TO DETERMINE IN WHICH ROUTE OF A RAPID INTERMEDIATE MEMORY IN THE MEMORY HIERARCHY OF A COMPUTER MEMORY (CACHE) ASSOCIATIVE BY SET OF TWO WAYS IS FOUND A SPECIFIC DATA.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ES9601212A ES2128938B1 (en) 1996-07-01 1996-07-01 PROCEDURE TO DETERMINE IN WHICH ROUTE OF A RAPID INTERMEDIATE MEMORY IN THE MEMORY HIERARCHY OF A COMPUTER MEMORY (CACHE) ASSOCIATIVE BY SET OF TWO WAYS IS FOUND A SPECIFIC DATA.

Publications (2)

Publication Number Publication Date
ES2128938A1 true ES2128938A1 (en) 1999-05-16
ES2128938B1 ES2128938B1 (en) 2000-02-01

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Family Applications (1)

Application Number Title Priority Date Filing Date
ES9601212A Expired - Fee Related ES2128938B1 (en) 1996-07-01 1996-07-01 PROCEDURE TO DETERMINE IN WHICH ROUTE OF A RAPID INTERMEDIATE MEMORY IN THE MEMORY HIERARCHY OF A COMPUTER MEMORY (CACHE) ASSOCIATIVE BY SET OF TWO WAYS IS FOUND A SPECIFIC DATA.

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ES (1) ES2128938B1 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5014195A (en) * 1990-05-10 1991-05-07 Digital Equipment Corporation, Inc. Configurable set associative cache with decoded data element enable lines
US5210843A (en) * 1988-03-25 1993-05-11 Northern Telecom Limited Pseudo set-associative memory caching arrangement
US5353424A (en) * 1991-11-19 1994-10-04 Digital Equipment Corporation Fast tag compare and bank select in set associative cache
WO1996006390A2 (en) * 1994-08-11 1996-02-29 Intel Corporation A two-way set-associative cache memory

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5210843A (en) * 1988-03-25 1993-05-11 Northern Telecom Limited Pseudo set-associative memory caching arrangement
US5014195A (en) * 1990-05-10 1991-05-07 Digital Equipment Corporation, Inc. Configurable set associative cache with decoded data element enable lines
US5353424A (en) * 1991-11-19 1994-10-04 Digital Equipment Corporation Fast tag compare and bank select in set associative cache
WO1996006390A2 (en) * 1994-08-11 1996-02-29 Intel Corporation A two-way set-associative cache memory

Also Published As

Publication number Publication date
ES2128938B1 (en) 2000-02-01

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