ES2116852A1 - Sincronizacion del acceso a memoria en multiprocesadores vectoriales. - Google Patents

Sincronizacion del acceso a memoria en multiprocesadores vectoriales.

Info

Publication number
ES2116852A1
ES2116852A1 ES09401905A ES9401905A ES2116852A1 ES 2116852 A1 ES2116852 A1 ES 2116852A1 ES 09401905 A ES09401905 A ES 09401905A ES 9401905 A ES9401905 A ES 9401905A ES 2116852 A1 ES2116852 A1 ES 2116852A1
Authority
ES
Spain
Prior art keywords
vectorial
access
multiprocessors
synchronization
memory access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
ES09401905A
Other languages
English (en)
Other versions
ES2116852B1 (es
Inventor
Cortes Mateo Valero
Guardia Montse Peiron
Parra Eduard Ayguade
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Universitat Politecnica de Catalunya UPC
Original Assignee
Universitat Politecnica de Catalunya UPC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Universitat Politecnica de Catalunya UPC filed Critical Universitat Politecnica de Catalunya UPC
Priority to ES9401905A priority Critical patent/ES2116852B1/es
Publication of ES2116852A1 publication Critical patent/ES2116852A1/es
Application granted granted Critical
Publication of ES2116852B1 publication Critical patent/ES2116852B1/es
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Multi Processors (AREA)
  • Complex Calculations (AREA)

Abstract

SINCRONIZACION DEL ACCESO A MEMORIA EN MULTIPROCESADORES VECTORIALES. EN SISTEMAS MULTIPROCESADORES VECTORIALES, LAS COLISIONES EN LA RED DE INTERCONEXION Y EN LOS MODULOS DE MEMORIA PROVOCAN QUE LA LATENCIA DE LOS ACCESOS AUMENTE ARBITRARIAMENTE, DANDO LUGAR A UNA IMPORTANTE PERDIDA DE EFICIENCIA DEL SISTEMA. NUESTRA PROPUESTA CONSISTE EN UNA SINCRONIZACION DEL ACCESO AL SISTEMA DE MEMORIA POR PARTE DE LOS DISTINTOS PROCESADORES DE MANERA QUE SE CONSIGUE ACCEDER A VECTORES CON LA MENOR LATENCIA POSIBLE SI EL ACCESO SE REALIZA FUERA DE ORDEN. EL METODO SE PUEDE APLICAR A LOS VECTORES QUE APARECEN MAS FRECUENTEMENTE EN PROGRAMAS REALES. LA CIRCUITERIA NECESARIA PARA LA IMPLEMENTACION DEL METODO ES DE COMPLEJIDAD SIMILAR A LA REQUERIDA PARA UN ACCESO CONVENCIONAL.
ES9401905A 1994-08-29 1994-08-29 Sincronizacion del acceso a memoria en multiprocesadores vectoriales. Expired - Fee Related ES2116852B1 (es)

Priority Applications (1)

Application Number Priority Date Filing Date Title
ES9401905A ES2116852B1 (es) 1994-08-29 1994-08-29 Sincronizacion del acceso a memoria en multiprocesadores vectoriales.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ES9401905A ES2116852B1 (es) 1994-08-29 1994-08-29 Sincronizacion del acceso a memoria en multiprocesadores vectoriales.

Publications (2)

Publication Number Publication Date
ES2116852A1 true ES2116852A1 (es) 1998-07-16
ES2116852B1 ES2116852B1 (es) 1999-03-16

Family

ID=8287390

Family Applications (1)

Application Number Title Priority Date Filing Date
ES9401905A Expired - Fee Related ES2116852B1 (es) 1994-08-29 1994-08-29 Sincronizacion del acceso a memoria en multiprocesadores vectoriales.

Country Status (1)

Country Link
ES (1) ES2116852B1 (es)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0047842A2 (en) * 1980-09-15 1982-03-24 International Business Machines Corporation Skewed matrix address generator
US4661900A (en) * 1983-04-25 1987-04-28 Cray Research, Inc. Flexible chaining in vector processor with selective use of vector registers as operand and result registers
EP0282070A2 (en) * 1987-03-13 1988-09-14 Fujitsu Limited Vector access to memories
WO1991019257A1 (en) * 1990-06-01 1991-12-12 Cray Research, Inc. Method and apparatus for sharing memory in a multiprocessor system
WO1992007335A1 (en) * 1990-10-19 1992-04-30 Cray Research, Inc. A scalable parallel vector computer system
US5142638A (en) * 1989-02-07 1992-08-25 Cray Research, Inc. Apparatus for sharing memory in a multiprocessor system
US5202970A (en) * 1989-02-07 1993-04-13 Cray Research, Inc. Method for sharing memory in a multiprocessor system

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0047842A2 (en) * 1980-09-15 1982-03-24 International Business Machines Corporation Skewed matrix address generator
US4661900A (en) * 1983-04-25 1987-04-28 Cray Research, Inc. Flexible chaining in vector processor with selective use of vector registers as operand and result registers
EP0282070A2 (en) * 1987-03-13 1988-09-14 Fujitsu Limited Vector access to memories
US5142638A (en) * 1989-02-07 1992-08-25 Cray Research, Inc. Apparatus for sharing memory in a multiprocessor system
US5202970A (en) * 1989-02-07 1993-04-13 Cray Research, Inc. Method for sharing memory in a multiprocessor system
WO1991019257A1 (en) * 1990-06-01 1991-12-12 Cray Research, Inc. Method and apparatus for sharing memory in a multiprocessor system
WO1992007335A1 (en) * 1990-10-19 1992-04-30 Cray Research, Inc. A scalable parallel vector computer system

Also Published As

Publication number Publication date
ES2116852B1 (es) 1999-03-16

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