EP4772004A1 - Transistors à effet de champ à jonction de grille à semi-conducteur à oxyde métallique au carbure de silicium verticaux - Google Patents

Transistors à effet de champ à jonction de grille à semi-conducteur à oxyde métallique au carbure de silicium verticaux

Info

Publication number
EP4772004A1
EP4772004A1 EP24768436.8A EP24768436A EP4772004A1 EP 4772004 A1 EP4772004 A1 EP 4772004A1 EP 24768436 A EP24768436 A EP 24768436A EP 4772004 A1 EP4772004 A1 EP 4772004A1
Authority
EP
European Patent Office
Prior art keywords
gate
jfet
mos gate
vertical
vertical sic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP24768436.8A
Other languages
German (de)
English (en)
Inventor
Kuo-Chang Robert Yang
Kamal Raj Varadarajan
Sorin S. Georgescu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Power Integrations Inc
Original Assignee
Power Integrations Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Power Integrations Inc filed Critical Power Integrations Inc
Publication of EP4772004A1 publication Critical patent/EP4772004A1/fr
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/83—FETs having PN junction gate electrodes
    • H10D30/831—Vertical FETs having PN junction gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/611—Insulated-gate field-effect transistors [IGFET] having multiple independently-addressable gate electrodes influencing the same channel
    • H10D30/615—Insulated-gate field-effect transistors [IGFET] having multiple independently-addressable gate electrodes influencing the same channel comprising a MOS gate electrode and at least one non-MOS gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/63—Vertical IGFETs
    • H10D30/635—Vertical IGFETs having no inversion channels, e.g. vertical accumulation channel FETs [ACCUFET] or normally-on vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/343—Gate regions of field-effect devices having PN junction gates

Landscapes

  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

L'invention concerne des transistors à effet de champ à jonction de grille (JFET) à semi-conducteur à oxyde métallique (MOS) à carbure de silicium verticaux (SiC). Une région épitaxiale (104) est développée sur une couche de substrat pour former une structure verticale. Un JFET vertical est formé à l'intérieur de la structure verticale et comprend une région de source (108) au niveau d'une surface de dispositif, une grille profonde (106) formée au-dessous de la surface, et un drain (102) formé par une couche de substrat. Une grille MOS (123) est formée au-dessus d'une région d'implant de canal de sous-surface pour améliorer le comportement de pincement et la résistance à l'état passant spécifique. La tension de pincement est déterminée, au moins en partie, par une épaisseur diélectrique de grille, une dimension de la hampe de JFET et une concentration de dopage de la région d'implant de canal de sous-surface.
EP24768436.8A 2023-09-01 2024-08-16 Transistors à effet de champ à jonction de grille à semi-conducteur à oxyde métallique au carbure de silicium verticaux Pending EP4772004A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US202363579972P 2023-09-01 2023-09-01
PCT/US2024/042689 WO2025049133A1 (fr) 2023-09-01 2024-08-16 Transistors à effet de champ à jonction de grille à semi-conducteur à oxyde métallique au carbure de silicium verticaux

Publications (1)

Publication Number Publication Date
EP4772004A1 true EP4772004A1 (fr) 2026-07-08

Family

ID=92711351

Family Applications (1)

Application Number Title Priority Date Filing Date
EP24768436.8A Pending EP4772004A1 (fr) 2023-09-01 2024-08-16 Transistors à effet de champ à jonction de grille à semi-conducteur à oxyde métallique au carbure de silicium verticaux

Country Status (4)

Country Link
EP (1) EP4772004A1 (fr)
KR (1) KR20260057424A (fr)
CN (1) CN121816839A (fr)
WO (1) WO2025049133A1 (fr)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3216804B2 (ja) * 1998-01-06 2001-10-09 富士電機株式会社 炭化けい素縦形ｆｅｔの製造方法および炭化けい素縦形ｆｅｔ
CN106783851B (zh) * 2017-01-19 2023-12-29 江苏紫峰知识产权服务有限公司 集成肖特基二极管的SiCJFET器件及其制作方法
WO2021202228A1 (fr) * 2020-03-29 2021-10-07 Power Integrations, Inc. Transistors à effet de champ à jonction en carbure de silicium

Also Published As

Publication number Publication date
KR20260057424A (ko) 2026-04-28
WO2025049133A1 (fr) 2025-03-06
CN121816839A (zh) 2026-04-07

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