EP4700757A1

EP4700757A1 - Voltage control method, device, and storage medium

Info

Publication number: EP4700757A1
Application number: EP24822324.0A
Authority: EP
Inventors: Linhong HAN; Yi Su; Haiming HE
Original assignee: Honor Device Co Ltd
Current assignee: Honor Device Co Ltd
Priority date: 2023-06-12
Filing date: 2024-03-19
Publication date: 2026-02-25
Also published as: WO2024255367A1; WO2024255367A9; CN119132229A

Abstract

Embodiments of this application provide a voltage control method, a device, and a storage medium, which are applied to the field of terminal technologies. The method is applied to an electronic device having a pixel circuit. The pixel circuit includes a drive module. A control end of the drive module is connected to a first node, and a source end of the drive module is connected to a second node. The method includes: when driving to display a first area of a first frame of image, controlling a voltage of the first node to be a first voltage, and controlling a voltage of the second node to be a second voltage; and when driving to display a second area of the first frame of image, controlling the voltage of the first node to be a third voltage, and controlling the voltage of the second node to be a fourth voltage, where a voltage difference between the first voltage and the second voltage is greater than a voltage difference between the third voltage and the fourth voltage; and a refresh rate of the first area is a first refresh rate, a refresh rate of the second area is a second refresh rate, and the first refresh rate is less than the second refresh rate. In this way, a probability that a display panel of the electronic device blinks can be reduced.

Description

This application claims priority to Chinese Patent Application No. 202310695264.2, filed with the China National Intellectual Property Administration on June 12, 2023 and entitled "VOLTAGE CONTROL METHOD, DEVICE, AND STORAGE MEDIUM", which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

This application relates to the field of terminal technologies, and in particular, to a voltage control method, a device, and a storage medium.

BACKGROUND

With development of terminal technologies, an electronic device provides a function of displaying a dynamic image in an area of a display panel, and displaying a still image in another area of the display panel. To reduce power consumption of the electronic device, a refresh rate of the still image display area is less than a refresh rate of the dynamic image display area.
However, when the still image display area switches to display the dynamic image, or the dynamic image display area switches to display the still image, the display panel of the electronic device may blink.

SUMMARY

Embodiments of this application provide a voltage control method, a device, and a storage medium, which are applied to the field of terminal technologies. When a dynamic image is displayed, the image may be refreshed at a high refresh rate; and when a still image is displayed, the image may be refreshed at a low refresh rate. Therefore, a gate voltage of a driving thin film transistor in a pixel circuit is controlled to reduce a difference between a gate voltage that is of the driving thin film transistor in a light-emitting phase when the displayed image is refreshed at a low refresh rate and a gate voltage that is of the driving thin film transistor in the light-emitting phase when a displayed image is refreshed at a high refresh rate, to reduce a brightness difference between an in-plane still image display area and dynamic image display area of a display panel, thereby reducing a probability that the display panel blinks when a refresh rate of a display area is switched.
According to a first aspect, an embodiment of this application provides a voltage control method, applied to an electronic device having a pixel circuit. The pixel circuit includes a drive module, a control end of the drive module is connected to a first node, and a source end of the drive module is connected to a second node. The method includes:

when driving to display a first area of a first frame of image, controlling a voltage of the first node to be a first voltage, and controlling a voltage of the second node to be a second voltage; and
when driving to display a second area of the first frame of image, controlling the voltage of the first node to be a third voltage, and controlling the voltage of the second node to be a fourth voltage.

A voltage difference between the first voltage and the second voltage is greater than a voltage difference between the third voltage and the fourth voltage; and a refresh rate of the first area is a first refresh rate, a refresh rate of the second area is a second refresh rate, and the first refresh rate is less than the second refresh rate.
In this way, when the electronic device drives to display an image, a difference between a voltage difference between the first node and the second node that are in the drive module corresponding to the first area and a voltage difference between the first node and the second node that are in the drive module corresponding to the second area can be reduced.
In a possible implementation, the first voltage is greater than the third voltage, and/or the second voltage is less than the fourth voltage.
In this way, when the electronic device drives to display an image, a difference between a voltage difference between the first node and the second node that are in the drive module corresponding to the first area and a voltage difference between the first node and the second node that are in the drive module corresponding to the second area can be reduced.
In a possible implementation, the pixel circuit further includes a data writing unit, the data writing unit is connected to the second node, and the data writing unit is enabled when either the first area or the second area of the first frame of image is displayed. The method further includes:

when driving to display the first area of a second frame of image, controlling the voltage of the first node to be the first voltage, and controlling the voltage of the second node to be the second voltage, where the data writing unit is disabled when the first area of the second frame of image is displayed; and
when driving to display the second area of the second frame of image, controlling the voltage of the first node to be the third voltage, and controlling the voltage of the second node to be the fourth voltage, where the data writing unit is enabled when the second area of the second frame of image is displayed.

In this way, when the electronic device drives to display an image, a difference between a voltage difference between the first node and the second node that are in the drive module corresponding to the first area and a voltage difference between the first node and the second node that are in the drive module corresponding to the second area can be reduced.
In a possible implementation, the method further includes:

when driving to display the first area of a third frame of image, controlling the voltage of the first node to be the first voltage, and controlling the voltage of the second node to be the second voltage, where the data writing unit is disabled when the first area of the third frame of image is displayed; and
when driving to display the second area of the third frame of image, controlling the voltage of the first node to be the third voltage, and controlling the voltage of the second node to be the fourth voltage, where the data writing unit is enabled when the second area of the third frame of image is displayed.

when driving to display the first area of a fourth frame of image, controlling the voltage of the first node to be the third voltage, and controlling the voltage of the second node to be the fourth voltage, where the data writing unit is disabled when the first area of the fourth frame of image is displayed; and
when driving to display the second area of the fourth frame of image, controlling the voltage of the first node to be the third voltage, and controlling the voltage of the second node to be the fourth voltage, where the data writing unit is enabled when the second area of the fourth frame of image is displayed.

In this way, when the electronic device drives to display an image, power consumption of the electronic device can be reduced.
In a possible implementation, the pixel circuit further includes a data writing unit, the data writing unit is connected to the second node, and the data writing unit is enabled when either the first area or the second area of the first frame of image is displayed. The method further includes:

when driving to display the first area of a second frame of image, controlling the voltage of the first node to be the third voltage, and controlling the voltage of the second node to be the fourth voltage, where the data writing unit is disabled when the first area of the second frame of image is displayed; and
when driving to display the second area of the second frame of image, controlling the voltage of the first node to be the third voltage, and controlling the voltage of the second node to be the fourth voltage, where the data writing unit is enabled when the second area of the second frame of image is displayed.

In this way, when the electronic device drives to display an image, power consumption of the electronic device can be reduced.
In a possible implementation, the method further includes:

determining a start position and an end position of the first area based on an identifier of the pixel circuit corresponding to the first area; and
determining a start position and an end position of the second area based on an identifier of the pixel circuit corresponding to the second area.

In this way, when the electronic device drives to display an image, precision and integrity of image display can be improved.
In a possible implementation, the method further includes:
when driving to display a third area of the first frame of image, controlling the voltage of the first node to be the first voltage, and controlling the voltage of the second node to be the second voltage, where a refresh rate of the third area is a third refresh rate, and the third refresh rate is less than the second refresh rate.
In this way, an image can be displayed in a plurality of display areas, and use experience of the electronic device can be improved.
In a possible implementation, the drive module includes a driving thin film transistor DTFT, a drain end of the DTFT is connected to a third node, and the DTFT is configured to output a current to the third node under control of the first node.
The pixel circuit further includes:

a first reset unit, connected to the first node, and configured to load a first initialized voltage to the shown first node in response to a first reset signal;
a storage capacitor, where one end is connected to the first node, and the other end is connected to a power supply positive electrode;
a first light-emitting control unit, connected to the power supply positive electrode and the second node, and configured to load a first power supply voltage of the power supply positive electrode to the second node in response to a light-emitting control signal;
a threshold compensation unit, connected to the first node and the third node, and configured to conduct the third node and the first node in response to a first scanning signal;
a second light-emitting control unit, connected to the third node and a fourth node, and configured to conduct the third node and the fourth node in response to a light-emitting control signal;
a light-emitting element, where one end is connected to the fourth node, and the other end is connected to a power supply negative electrode to load a second power supply voltage of the power supply negative electrode;
a second reset unit, connected to the fourth node, and configured to load a second initialized voltage to the fourth node in response to a second reset signal;
a data writing unit, connected to the second node, and configured to load a data voltage to the second node in response to a second scanning signal; and
a third reset unit, connected to the second node, and configured to load a third initialized voltage to the second node in response to the second reset signal.

In this way, when the electronic device drives to display an image, a difference between a voltage difference between the first node and the second node that are in the drive module corresponding to the first area and a voltage difference between the first node and the second node that are in the drive module corresponding to the second area can be reduced, thereby reducing a probability that a display panel of the electronic device blinks.
In a possible implementation, the first reset unit includes a first reset transistor, the first light-emitting control unit includes a first light-emitting control transistor, the threshold compensation unit includes a threshold compensation transistor, the second light-emitting control unit includes a second light-emitting control transistor, the light-emitting element includes an organic light-emitting diode OLED, the second reset unit includes a second reset transistor, the data writing unit includes a data writing transistor, and the third reset unit includes a third reset transistor.
In this way, when the electronic device drives to display an image, a difference between a voltage difference between the first node and the second node that are in the drive module corresponding to the first area and a voltage difference between the first node and the second node that are in the drive module corresponding to the second area can be reduced, thereby reducing a probability that a display panel of the electronic device blinks.
According to a second aspect, an embodiment of this application provides an electronic device, including a processor, a display driver integrated circuit DDIC, a pixel circuit, and a memory.
The memory stores computer-executable instructions.
The processor indicates the display driver integrated circuit to drive the pixel circuit.
The display driver integrated circuit executes the computer-executable instructions stored in the memory, to enable the electronic device to perform the method according to the first aspect, and drive the pixel circuit.
According to a third aspect, an embodiment of this application provides a computer-readable storage medium, and the computer-readable storage medium stores a computer program. The computer program is executed by the display driver integrated circuit DDIC to implement the method according to the first aspect.
According to a fourth aspect, an embodiment of this application provides a computer program product, and the computer program product includes a computer program. When the computer program is run, a computer is enabled to perform the method according to the first aspect.
According to a fifth aspect, an embodiment of this application provides a chip. The chip includes a processor, and the processor is configured to invoke a computer program in a memory to perform the method according to the first aspect.
It should be understood that the technical solutions of the second aspect to the fifth aspect of this application correspond to the technical solutions of the first aspect of this application, and beneficial effects achieved by the aspects and corresponding feasible implementations are similar. Details are not described herein again.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a schematic diagram of a structure of a display panel according to an embodiment of this application;
FIG. 2 is a first schematic diagram of a pixel circuit according to an embodiment of this application;
FIG. 3 is a first schematic diagram of a time sequence of levels of signals according to an embodiment of this application;
FIG. 4A to FIG. 4C are a diagram of comparison between quantities of times of enabling a transistor T4 in a high-frequency display area and a low-frequency display area when an electronic device refreshes an image according to an embodiment of this application;
FIG. 5 is a diagram of a time sequence of levels of corresponding signals in a low-frequency display area and a first schematic diagram of initialized voltages according to an embodiment of this application;
FIG. 6 is a diagram of a time sequence of levels of corresponding signals in a high-frequency display area and a schematic diagram of initialized voltages according to an embodiment of this application;
FIG. 7 is a first diagram of a time sequence of a bias voltage generated when an electronic device refreshes an image according to an embodiment of this application;
FIG. 8 is a second diagram of a time sequence of a bias voltage generated when an electronic device refreshes an image according to an embodiment of this application;
FIG. 9 is a diagram of a time sequence of levels of corresponding signals in a low-frequency display area and a second schematic diagram of initialized voltages according to an embodiment of this application;
FIG. 10 is a third diagram of a time sequence of a bias voltage generated when an electronic device refreshes an image according to an embodiment of this application;
FIG. 11 is a fourth diagram of a time sequence of a bias voltage generated when an electronic device refreshes an image according to an embodiment of this application;
FIG. 12 is a diagram of a time sequence of levels of corresponding signals in a low-frequency display area and a third schematic diagram of initialized voltages according to an embodiment of this application;
FIG. 13 is a fifth diagram of a time sequence of a bias voltage generated when an electronic device refreshes an image according to an embodiment of this application;
FIG. 14 is a sixth diagram of a time sequence of a bias voltage generated when an electronic device refreshes an image according to an embodiment of this application;
FIG. 15 is a second schematic diagram of a pixel circuit according to an embodiment of this application;
FIG. 16 is a schematic diagram of a structure of an electronic device 100 according to an embodiment of this application; and
FIG. 17 is a block diagram of a software structure of an electronic device 100 according to an embodiment of this application.

DESCRIPTION OF EMBODIMENTS

To clearly describe the technical solutions in the embodiments of this application, the following briefly describes some terms and technologies in the embodiments of this application.

1. Some Terms

In the embodiments of this application, words such as "first" and "second" are used to distinguish between same items or similar items with basically same functions and effects. For example, a first chip and a second chip are merely used to distinguish between different chips, and are not intended to limit a sequence of the first chip and the second chip. A person skilled in the art may understand that the words such as "first" and "second" do not limit a quantity or an execution sequence, and the words such as "first" and "second" do not define a definite difference.
It should be noted that the words such as "example" or "for example" in the embodiments of this application are used to indicate an example, an illustration, or a description. Any embodiment or design solution described as "example" or "for example" in this application should not be construed as being preferred or advantageous over other embodiments or design solutions. Exactly, use of the words such as "example" or "for example" is intended to present a related concept in a specific manner.
In the embodiments of this application, "at least one" means one or more, and "a plurality of" means two or more. "And/Or" describes an association relationship between associated objects, and represents that three relationships may exist. For example, "A and/or B" may represent the following cases: Only A exists, both A and B exist, and only B exists, where A and B may be singular or plural. The character "/" usually indicates an "or" relationship between associated objects. "At least one of the following items" or a similar expression thereof means any combination of these items, including a single item or any combination of a plurality of items. For example, at least one of a, b, or c may represent a, b, c, a-b, a--c, b-c, or a-b-c, where a, b, and c may be singular or plural.
It should be noted that in the embodiments of this application, "when ..." may be an instantaneous occurrence time of a case, or may be a period of time after occurrence of a case, and this is not specifically limited in the embodiments of this application. In addition, a display interface provided in the embodiments of this application is merely an example, and the display interface may further include more or less content.

2. Electronic device

The electronic device in the embodiments of this application may include a handheld device with an image processing function, an onboard device, or the like. For example, some electronic devices are a mobile phone (mobile phone), a tablet computer, a palmtop computer, a notebook computer, a mobile internet device (mobile internet device, MID), a wearable device, a virtual reality (virtual reality, VR) device, an augmented reality (augmented reality, AR) device, a wireless terminal in industrial control (industrial control), a wireless terminal in self driving (self driving), a wireless terminal in a remote medical surgery (remote medical surgery), a wireless terminal in a smart grid (smart grid), a wireless terminal in transportation safety (transportation safety), a wireless terminal in a smart city (smart city), a wireless terminal in a smart home (smart home), a cellular phone, a cordless phone, a session initiation protocol (session initiation protocol, SIP) phone, a wireless local loop (wireless local loop, WLL) station, a personal digital assistant (personal digital assistant, PDA), a handheld device with a wireless communication function, a computing device or another processing device connected to a wireless modem, an onboard device, a wearable device, a terminal device in a 5G network, a terminal device in a future evolved public land mobile network (public land mobile network, PLMN), and the like. This is not limited in the embodiments of this application.
As an example rather than a limitation, in the embodiments of this application, the electronic device may alternatively be a wearable device. The wearable device may also be referred to as a wearable smart device, and is a generic term for wearable devices such as hearing aid, glasses, gloves, watches, clothing, and shoes that are intelligently designed and developed from daily wear by using wearable technologies. The wearable device is a portable device that is worn directly on a body or integrated into clothing or an accessory of a user. The wearable device is not merely a hardware device, but implements powerful functions through software support, data exchange, and cloud interaction. In a broad sense, the wearable smart device includes a full-featured and large-size device that can implement all or some of functions without relying on a smartphone, for example a smartwatch or smart glasses, and a device that focuses only on a specific type of application function and needs to be used together with another device such as a smartphone, for example, various types of smart bands and smart jewelry that monitor physical signs.
In addition, in the embodiments of this application, the electronic device may alternatively be a terminal device in an internet of things (internet of things, IoT) system. IoT is an important part in future development of information technologies, and a main technical feature thereof is connecting a thing to a network through a communication technology, to implement an intelligent network of human-machine interconnection and interconnection between things.
The electronic device in the embodiments of this application may also be referred to as user equipment (user equipment, UE), a mobile station (mobile station, MS), a mobile terminal (mobile terminal, MT), an access terminal, a subscriber unit, a subscriber station, a mobile station, a mobile console, a remote station, a remote terminal, a mobile device, a user terminal, a terminal, a wireless communication device, a user agent, a user apparatus, or the like.
In the embodiments of this application, the electronic device or each network device includes a hardware layer, an operating system layer that runs above the hardware layer, and an application layer that runs above the operating system layer. The hardware layer includes hardware such as a central processing unit (central processing unit, CPU), a memory management unit (memory management unit, MMU), and a memory (also referred to as a main memory). The operating system may be any one or more computer operating systems for implementing service processing through a process (process), for example, a Linux operating system, a Unix operating system, an Android operating system, an iOS operating system, or a windows operating system. The application layer includes applications such as Browser, Contacts, word processing software, and instant messaging software.
In a possible implementation, the electronic device includes a display panel. FIG. 1 is a schematic diagram of a structure of a display panel. As shown in FIG. 1, the display panel includes a light-emitting control signal generation unit, a first reset signal generation unit, a second scanning signal generation unit, a display area of a displayed image, a second scanning signal generation unit, a first scanning signal generation unit, a second reset signal generation unit, and a display driver integrated circuit (display driver integrated circuit, DDIC). The display area includes a plurality of pixel circuits in an array. The light-emitting control signal generation unit, the first reset signal generation unit, the second scanning signal generation unit, the display area of the displayed image, the second scanning signal generation unit, the first scanning signal generation unit, the second reset signal generation unit, and the display driver integrated circuit may all transmit their respective corresponding signals to the pixel circuits by using leads. The display driver integrated circuit may control transmission of the signals respectively corresponding to the light-emitting control signal generation unit, the first reset signal generation unit, the second scanning signal generation unit, the display area of the displayed image, the second scanning signal generation unit, the first scanning signal generation unit, and the second reset signal generation unit. The pixel circuit includes a driving thin film transistor and a light-emitting element. The driving thin film transistor is configured to drive the light-emitting element to emit light. The light-emitting element may be used as a sub-pixel of the display panel. The electronic device drives and controls the pixel circuit corresponding to the display area, to implement a function of displaying a dynamic image and a still image on the display panel.
The display area may include a high-frequency display area and a low-frequency display area. An image is refreshed at a high refresh rate in the high-frequency display area, and an image is refreshed at a low refresh rate in the low-frequency display area. When a dynamic image is displayed, the image may be refreshed at a high refresh rate. When a still image is displayed, the image may be refreshed at a low refresh rate. In a possible implementation, in a case of a same data voltage, brightness of a display area with a low refresh rate is different from brightness of a display area with a high refresh rate. When a refresh rate of the display area is switched from a low refresh rate to a high refresh rate or the refresh rate of the display area is switched from the high refresh rate to the low refresh rate, a blinking phenomenon occurs in the display area in which the refresh rate is switched, and the display panel of the electronic device blinks.
In view of this, the embodiments of this application provide a voltage control method. A gate voltage of a driving thin film transistor is controlled to reduce a difference between a gate voltage of the driving thin film transistor during low-frequency display and a gate voltage of the driving thin film transistor during high-frequency display, to reduce a brightness difference between an in-plane high-frequency display area and low-frequency display area of a display panel, thereby reducing a probability that the display panel blinks when a refresh rate of a display area is switched.
The voltage control method provided in the embodiments of this application is described below with reference to some embodiments.
FIG. 2 is a first schematic diagram of a pixel circuit according to an embodiment of this application. As shown in FIG. 2, the pixel circuit includes a plurality of thin film transistors (thin film transistor, TFT), a capacitor C1, and a light-emitting element. The light-emitting element may include an organic light-emitting diode (organic light-emitting diode, OLED).
In this embodiment of this application, the thin film transistor may be referred to as a transistor or a TFT transistor for short.
The plurality of thin film transistors are, for example, a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, and a transistor T8 shown in FIG. 2.
The transistor T3 is a driving thin film transistor (driving TFT, DTFT) that drives the light-emitting element to emit light. The transistor T2 is a compensation transistor that controls charging of the capacitor C1 and conduction of the transistor T3. The transistors T1 and T2 may include oxide transistors. The other transistors may include transistors using a low temperature poly-silicon (low temperature poly-silicon, LTPS) technology.
As shown in FIG. 2, the transistor T1 is connected to a first node N1, and is configured to load a first initialized voltage to the shown first node N1 in response to a first reset signal. The first reset signal may be referred to as ResetN. The first initialized voltage may be referred to as Vinit 1.
One end of the capacitor C1 is connected to the first node N1, and the other end is connected to a power supply positive electrode VDD. The first node N1 may be referred to as an N1 node or an N1 point.
The transistor T5 is connected to the power supply positive electrode VDD and a second node N2, and is configured to load a first power supply voltage of the power supply positive electrode VDD to the second node N2 in response to a light-emitting control signal. The light-emitting control signal may be referred to as EM. The second node N2 may be referred to as an N2 node or an N2 point.
The transistor T3 is connected to the first node N1, the second node N2, and a third node N3, and is configured to output a current to the third node N3 under control of the first node N1. The third node N3 may be referred to as an N3 node or an N3 point.
The transistor T2 is connected to the first node N1 and the third node N3, and is configured to conduct the third node N3 and the first node N1 in response to a first scanning signal. The first scanning signal may be referred to as GateN.
The transistor T6 is connected to the third node N3 and a fourth node N4, and is configured to connect the third node N3 to the fourth node N4 in response to a light-emitting control signal.
One end of the light-emitting element is connected to the fourth node N4, and the other end is connected to a power supply negative electrode VSS to load a second power supply voltage of the power supply negative electrode VSS.
The transistor T7 is connected to the fourth node N4, and is configured to load a second initialized voltage to the fourth node N4 in response to a second reset signal. The second reset signal may be referred to as ResetP. The second initialized voltage may be referred to as Vinit2.
The transistor T4 is connected to the second node N2, and is configured to load a data voltage to the second node N2 in response to a second scanning signal. The second scanning signal may be referred to as GateP. The data voltage may be referred to as Vdata.
The transistor T8 is connected to the second node N2, and is configured to load a third initialized voltage to the second node N2 in response to the second reset signal. The third initialized voltage may be referred to as Vinit3.
In this embodiment of this application, a "conducted" state of a transistor refers to a state in which a source and a drain of the transistor are electrically connected, and a "cutoff" state of a transistor refers to a state in which a source and a drain of the transistor are electrically disconnected. It may be understood that when a transistor is cut off, the transistor may still have a leakage current. A conduction condition of the transistors T1 and T2 is Vgs>Vth. A conduction condition of the remaining transistors is Vgs<Vth. A high level in this embodiment of this application may meet the conduction condition of the transistors T1 and T2, and a low level in this embodiment of this application may meet the conduction condition of the remaining transistors. That the transistor T4 is conducted and a data voltage is loaded to the second node N2 may be referred to as that the transistor T4 is enabled. That the transistor T4 is not conducted or the transistor T4 is in the cutoff state, and a data voltage is not loaded to the second node N2 may be referred to as that the transistor T4 is disabled. That the transistor T2 is conducted may be referred to as that the transistor T2 is enabled. That the transistor T2 is not conducted or the transistor T2 is in the cutoff state may be referred to as that the transistor T2 is disabled. That the transistor T1 is conducted may be referred to as that the transistor T1 is enabled. That the transistor T1 is not conducted or the transistor T1 is in the cutoff state may be referred to as that the transistor T1 is disabled.
When an electronic device refreshes a frame of image to display the frame of image on a display panel, the electronic device may drive and control the pixel circuit in a row-based driving manner, or may drive and control the pixel circuit in a column-based driving manner. Principles of the two manners are similar. An example in which the electronic device drives and controls the pixel circuit in the row-based driving manner is used below for description.
Each time the electronic device refreshes a frame of image, working of the pixel circuit may include a reset phase, a writing phase, a light-emitting waiting phase, and a light-emitting phase.
FIG. 3 is a first schematic diagram of a time sequence of levels of signals according to an embodiment of this application. With reference to FIG. 2 and FIG. 3, the following describes phases in which the pixel circuit works when the electronic device refreshes a frame of image.
When the electronic device refreshes a frame of image, if the transistors T1, T4, and T2 are enabled, phases that corresponds to a display area of the frame of image and in which the pixel circuit works are shown in (1.1)-(1.4).

(1.1) Reset phase:

The light-emitting control signal (EM) is at a high level. The transistor T5 and the transistor T6 are in a cutoff state.
The first reset signal (ResetN) changes from a low level to a high level. The high level of the first reset signal conducts the transistor T1.
The second reset signal (ResetP) changes from a high level to a low level, and then changes from the low level to the high level. Start time of the low level of the second reset signal (ResetP) is earlier than start time of the high level of the first reset signal (ResetN). The low level of the second reset signal conducts the transistors T8 and T7.
The first scanning signal (GateN) changes from a high level to a low level, and then changes from the low level to the high level. Both start time and end time of the low level are located in a time period of the high level of the first reset signal. The high level of the first scanning signal conducts the transistor T2, to further conduct the N1 node and to the N3 node.
The second scanning signal (GateP) is at a high level. The transistor T4 is in a cutoff state.
The conducted transistor T1 loads the first initialized voltage Vinit1 to the N1 point, to reset the N1 point and clear a potential written into a previous frame. Therefore, the first initialized voltage Vinit1 is also written into the capacitor C1. The conducted transistor T2 further loads the first initialized voltage Vinit1 to the N3 point, to reset the N3 point and clear a residual signal that may exist in a previous phase.
The conducted transistor T8 loads the third initialized voltage Vinit3 to the N2 point, to write an initial state voltage Vinit3 into the N2 point. In this case, a voltage difference Vgs between a gate and a source of the transistor T3 is a voltage difference between the N1 point and the N2 point. In other words, in this case, Vgs is a voltage difference between Vinit1 and Vinit3. In this case, Vgs is greater than a threshold voltage Vth of the transistor T3, so that the transistor T3 is not conducted.
The conducted transistor T7 loads the second initialized voltage Vinit2 to the N4 point, to write an initial state voltage Vinit2 into the N4 point.

(1.2) Writing phase:

The light-emitting control signal (EM) remains at a high level. The transistor T5 and the transistor T6 are in a cutoff state.
The first reset signal (ResetN) changes from a high level to a low level, so that the transistor T1 is in a cutoff state.
The second reset signal (ResetP) remains at a high level. Both the transistor T8 and the transistor T7 are in a cutoff state.
The first scanning signal (GateN) remains at a high level. The high level of the first scanning signal (GateN) conducts the transistor T2, to further conduct N1 and N3.
The second scanning signal (GateP) changes from a high level to a low level, and then changes from the low level to the high level. The low level of the second scanning signal (GateP) conducts the transistor T4. The conducted transistor T4 loads the data voltage Vdata to the N2 node. The capacitor C1 may discharge electricity to the transistor T3, so that the transistor T3 is conducted. Therefore, the conducted transistor T4 may feed back the data voltage Vdata to N1 by using the transistors T3 and T2, and charge the capacitor C1. A voltage at the N1 point is Vdata+Vth. Vth is a threshold voltage of the transistor T3. When the transistor T4 is conducted, a voltage at the N2 point is Vdata.

(1.3) Light-emitting waiting phase:

The light-emitting control signal (EM) remains at a high level. The transistor T5 and the transistor T6 are in a cutoff state.
The first reset signal (ResetN) remains at a low level, and the transistor T1 is in a cutoff state.
The second reset signal (ResetP) changes from a high level to a low level, and then changes from the low level to the high level. The low level of the second reset signal conducts the transistors T8 and T7. The high level of the second reset signal enables both the transistor T8 and the transistor T7 to be in a cutoff state.
The first scanning signal (GateN) is at a low level, so that the transistor T2 is in a cutoff state.
The second scanning signal (GateP) remains at a high level. The transistor T4 is in a cutoff state.
The conducted transistor T8 loads the third initialized voltage Vinit3 to the N2 point, to write an initial state voltage Vinit3 into the N2 point.
The conducted transistor T7 loads the second initialized voltage Vinit2 to the N4 point, to write an initial state voltage Vinit2 into the N4 point. In this way, it is convenient to reset the light-emitting element before the light-emitting element emits light, thereby reducing impact caused by a signal that may remain in a previous stage in emitting light by the light-emitting element.
The capacitor C1 may discharge electricity to the transistor T3. A voltage difference between a gate and a source of the transistor T3 is greater than a threshold voltage Vth of the transistor T3, and the transistor T3 is not conducted.

(1.4) Light-emitting phase:

The capacitor C1 may maintain an N1 voltage of the transistor T3.
The light-emitting control signal (EM) changes from a high level to a low level. The low level of the light-emitting control signal conducts the transistor T5 and the transistor T6. The first power supply voltage of the power supply positive electrode (VDD) is written into the N2 node, Vgs of the transistor T3 is less than Vth, and the transistor T3 is conducted.
The first reset signal (ResetN) remains at a low level. The transistor T1 is in a cutoff state.
The second reset signal (ResetP) remains at a high level. The transistors T7 and T8 are in a cutoff state.
The first scanning signal (GateN) remains at a low level. The transistor T2 is in a cutoff state.
The second scanning signal (GateP) remains at a high level. The transistor T4 is in a cutoff state.
The conducted transistor T5 loads the first power supply voltage of the power supply positive electrode to the N2 point. The transistor T3 is conducted. The conducted transistor T6 conducts the N3 and N4 points. The second power supply voltage of the power supply negative electrode is loaded to one end of the light-emitting element. The light-emitting element starts to emit light.
When the light-emitting element emits light, the transistor T3 divides the voltage, so that brightness of the light-emitting element is controlled by the transistor T3. However, a voltage division status of the transistor T3 is affected by a gate voltage of the transistor T3, that is, the N1 voltage. For example, a larger voltage difference between a gate and a source of the transistor T3 indicates a smaller current flowing through the transistor T3. The light-emitting element is connected to the transistor T3 in series, a current flowing through the light-emitting element is smaller, and therefore brightness of the light-emitting element is lower.
When the electronic device refreshes a frame of image, if the transistors T1, T4, and T2 are disabled, phases that corresponds to a display area of the frame of image and in which the pixel circuit works are shown in (2.1)-(2.4).

(2.1) Reset phase:

The light-emitting control signal (EM) is at a high level. The transistor T5 and the transistor T6 are in a cutoff state.
The first reset signal (ResetN) remains at a low level. The transistor T1 remains in a cutoff state.
The second reset signal (ResetP) changes from a high level to a low level, and then changes from the low level to the high level. Similar to the reset phase shown in (1.1), the low level of the second reset signal conducts the transistors T8 and T7. The conducted transistor T8 loads the third initialized voltage Vinit3 to the N2 point, to write the third initialized voltage Vinit3 into the N2 point. The conducted transistor T7 loads the second initialized voltage Vinit2 to the N4 point, to write an initial state voltage Vinit2 into the N4 point.
The first scanning signal (GateN) remains at a low level. The transistor T2 is in a cutoff state.
The second scanning signal (GateP) is at a high level. The transistor T4 remains in a cutoff state.
The capacitor C1 may discharge electricity to the transistor T3, and the transistor T3 is in a cutoff state. A gate voltage of the transistor T3 is a voltage at the N1 point.

(2.2) Writing phase:

The light-emitting control signal (EM) remains at a high level. The transistor T5 and the transistor T6 are in a cutoff state.
The first reset signal (ResetN) remains at a low level. The transistor T1 is in a cutoff state.
The second reset signal (ResetP) remains at a high level. The transistors T7 and T8 are in a cutoff state.
The first scanning signal (GateN) remains at a low level. The transistor T2 is in a cutoff state.
The second scanning signal (GateP) remains at a high level. The transistor T4 is in a cutoff state.
The capacitor C1 may discharge electricity to the transistor T3, and the transistor T3 is in a cutoff state. A gate voltage of the transistor T3 is a voltage at the N1 point.

(2.3) Light-emitting waiting phase:

The light-emitting control signal (EM) remains at a high level. The transistor T5 and the transistor T6 are in a cutoff state.
The first reset signal (ResetN) remains at a low level, and the transistor T1 is in a cutoff state.
The second reset signal (ResetP) changes from a high level to a low level, and then changes from the low level to the high level. The low level of the second reset signal conducts the transistors T8 and T7. The high level of the second reset signal enables both the transistor T8 and the transistor T7 to be in a cutoff state.
The first scanning signal (GateN) remains at a low level. The transistor T2 is in a cutoff state.
The second scanning signal (GateP) remains at a high level. The transistor T4 is in a cutoff state.
The conducted transistor T8 loads the third initialized voltage Vinit3 to the N2 point, to write an initial state voltage Vinit3 into the N2 point.
The conducted transistor T7 loads the second initialized voltage Vinit2 to the N4 point, to write an initial state voltage Vinit2 into the N4 point. In this way, it is convenient to reset the light-emitting element before the light-emitting element emits light, thereby reducing impact caused by a signal that may remain in a previous stage in emitting light by the light-emitting element.
The capacitor C1 may discharge electricity to the transistor T3, and the transistor T3 is in a cutoff state. A gate voltage of the transistor T3 is a voltage at the N1 point.

(2.4) Light-emitting phase:

The capacitor C1 may maintain an N1 voltage of the transistor T3.
The light-emitting control signal (EM) changes from a high level to a low level. The low level of the light-emitting control signal conducts the transistor T5 and the transistor T6. The first power supply voltage of the power supply positive electrode (VDD) is written into the N2 node, Vgs of the transistor T3 is less than Vth, and the transistor T3 is conducted.
The first reset signal (ResetN) remains at a low level. The transistor T1 remains in a cutoff state.
The second reset signal (ResetP) remains at a high level. The transistors T7 and T8 are in a cutoff state.
The first scanning signal (GateN) remains at a low level. The transistor T2 is in a cutoff state.
The second scanning signal (GateP) remains at a high level. The transistor T4 is in a cutoff state.
The conducted transistor T5 loads the first power supply voltage of the power supply positive electrode to the N2 point. The transistor T3 is conducted. The conducted transistor T6 conducts the N3 and N4 points. The second power supply voltage of the power supply negative electrode is loaded to one end of the light-emitting element. The light-emitting element starts to emit light.
When the light-emitting element emits light, the transistor T3 divides the voltage, so that brightness of the light-emitting element is controlled by the transistor T3. A voltage division status of the transistor T3 is affected by a voltage maintained at the N1 point by the capacitor C1. The voltage at the N1 point is affected by a potential of the capacitor C1. The potential of the capacitor C1 is a potential remaining at the end of a previous phase after the capacitor C1 discharges electricity. For example, a smaller voltage at the N1 point indicates a smaller voltage difference between the gate and the source of the transistor T3, and a larger current flowing through the transistor T3. The light-emitting element is connected to the transistor T3 in series, a current flowing through the light-emitting element is larger, and therefore brightness of the light-emitting element is higher.
It may be learned from the foregoing that, when the electronic device refreshes a frame of image, if the transistors T1, T4, and T2 corresponding to a display area are enabled, the capacitor C1 corresponding to the display area is charged in the reset phase.
When the electronic device refreshes a frame of image, if the transistors T1, T4, and T2 corresponding to a display area are disabled, the potential of the capacitor C1 corresponding to the display area always maintains the gate voltage of the transistor T3 in the reset phase, the writing phase, and the light-emitting phase, or the potential of the capacitor C1 corresponding to the display area is always in a discharging state in the reset phase, the writing phase, and the light-emitting phase, and is not charged. An initial voltage of the capacitor C1 corresponding to the display area is a voltage remaining after electricity is discharged in a previous frame.
Generally, when the electronic device refreshes an image, a refresh rate of a high-frequency display area is greater than a refresh rate of a low-frequency display area.
For ease of understanding, this embodiment of this application is described by using an example in which the refresh rate of the low-frequency display area is 10 Hz and the refresh rate of the high-frequency display area is 120 Hz.
The refresh rate may be equal to a quantity of times of enabling the transistors T1, T4, and T2 per unit time when the electronic device refreshes the image. A higher refresh rate indicates a large quantity of times of enabling the transistors T1, T4, and T2. Therefore, in a same time period, a quantity of times of enabling the transistors T1, T4, and T2 corresponding to the high-frequency display area is larger than a quantity of times of enabling the transistors T1, T4, and T2 corresponding to the low-frequency display area.
FIG. 4A to FIG. 4C are a diagram of comparison between quantities of times of enabling transistors T4 and T2 in a high-frequency display area and a low-frequency display area when an electronic device refreshes an image in one second. The low-frequency display area is a first area shown in FIG. 4A. The high-frequency display area is a second area shown in FIG. 4A. A refresh rate of the low-frequency display area or the first area is 120 Hz. A refresh rate of the high-frequency display area or the second area is 10 Hz.
It may be learned from FIG. 2 and FIG. 3 that, when the electronic device refreshes a frame of image, the transistors T1, T4, and T2 are enabled once or zero times. As shown in FIG. 4A to FIG. 4C, when the electronic device refreshes 120 frames of images in one second, the refresh rate of the high-frequency display area is 120 Hz, and the refresh rate of the low-frequency display area is 10 Hz. The transistors T1, T4, and T2 corresponding to the high-frequency display area are enabled 120 times in the high-frequency display area, the transistors T1, T4, and T2 corresponding to the low-frequency display area are enabled 10 times in the low-frequency display area, and 11 frames of images space two times of enabling apart. Image sequence numbers of the 120 frames of images refreshed by the electronic device in one second are F1, F2, ..., and F120 shown in FIG. 4B and FIG. 4C.
It may be learned from FIG. 2 and FIG. 3 that, when the electronic device refreshes a frame of image, if the transistors T1, T2, and T4 are corresponding to a display area of the frame of image are enabled, the capacitor C1 corresponding to the display area of the frame of image is charged in the writing phase. As shown in the embodiments shown in FIG. 2 and FIG. 3, when the electronic device refreshes the 120 frames of images in one second and the refresh rate of the high-frequency display area is 120 Hz, in one second, the capacitor C1 corresponding to the high-frequency display area is charged 120 times, or a frequency at which Vdata is written into the N1 point in the high-frequency display area is 120 Hz. When the electronic device refreshes the 120 frames of images in one second and the refresh rate of the low-frequency display area is 10 Hz, in one second, the capacitor C1 corresponding to the low-frequency display area is charged 10 times, or a frequency at which Vdata is written into the N1 point in the low-frequency display area is 10 Hz.
In a possible implementation, voltage values of the first initialized voltage, the second initialized voltage, and the third initialized voltage in the high-frequency display area are the same as voltage values of the first initialized voltage, the second initialized voltage, and the third initialized voltage in the low-frequency display area. With reference to FIG. 2, FIG. 3, and FIG. 4A to FIG. 4C, it may be learned that brightness of the high-frequency display area is different from brightness of the low-frequency display area as follows:
In the process in which the electronic device refreshes the 120 frames of images in one second, the refresh rate of the low-frequency display area is low, and a quantity of times that the capacitor C1 corresponding to the low-frequency display area is changed is small. Electricity charged to the capacitor C1 when the transistors T1, T4, and T2 are enabled needs to provide a gate voltage for the transistor T3 during display of a frame of image when the transistors T1, T4, and T2 are enabled and during display of 11 consecutive frames of images when the transistors T1, T4, and T2 are disabled subsequently. In the process in which the capacitor C1 provides the gate voltage for the transistor T3 during display of the 11 consecutive frames of images when the transistors T1, T4, and T2 are disabled, the capacitor C1 is always in a discharging state without being charged. A potential at the N1 point decreases as the capacitor C1 discharges electricity. When the light-emitting element emits light, the gate voltage of the transistor T3 becomes lower, and a voltage difference between the gate and the source of the transistor T3 becomes smaller. When the light-emitting element emits light, a current flowing through the transistor T3 becomes larger. The light-emitting element is connected to the transistor T3 in series, and a current flowing through the light-emitting element becomes larger, so that brightness of the light-emitting element becomes higher, and brightness of the low-frequency display area becomes higher.
Correspondingly, in the process in which the electronic device refreshes the 120 frames of images in one second, the refresh rate of the high-frequency display area is high, and a quantity of times that the capacitor C1 corresponding to the high-frequency display area is changed is large. In addition, electricity obtained by the capacitor C1 when the transistors T1, T4, and T2 are enabled needs to provide a gate voltage for the transistor T3 only during display of a frame of image when the transistors T1, T4, and T2 is enabled. When the light-emitting element emits light, a current flowing through the transistor T3 is small. The light-emitting element is connected to the transistor T3 in series, and a current flowing through the light-emitting element is small, so that brightness of the light-emitting element is low, and brightness of the high-frequency display area is low and brightness is constant.
It may be learned that, in a case in which the voltage values of the first initialized voltage, the second initialized voltage, and the third initialized voltage in the high-frequency display area are the same as the voltage values of the first initialized voltage, the second initialized voltage, and the third initialized voltage in the low-frequency display area, when the light-emitting element emits light or in the light-emitting phase, a difference between a gate voltage of the transistor T3 corresponding to the low-frequency display area and a gate voltage of the transistor T3 corresponding to the high-frequency display area is larger, and a difference between brightness of the low-frequency display area and brightness of the high-frequency display area is also larger. When a refresh rate of a display area is switched, a display panel of the electronic device blinks.
Therefore, when the electronic device refreshes an image, an amount of electricity charged, when the transistors T1, T4, and T2 are enabled, to the capacitor C1 corresponding to the low-frequency display area may be increased, to reduce the difference that is between the gate voltage of the transistor T3 corresponding to the low-frequency display area and the gate voltage of the transistor T3 corresponding to the high-frequency display area and that is generated when the light-emitting element emits light, or reduce the difference that is between the gate voltage of the transistor T3 corresponding to the low-frequency display area and the gate voltage of the transistor T3 corresponding to the high-frequency display area and that is generated in the light-emitting phase, so that the difference between the brightness of the low-frequency display area and that of the high-frequency display area can be reduced, thereby reducing a probability that the display panel of the electronic device blinks.
For this reason, FIG. 5 is a second schematic diagram of a time sequence of levels of signals according to an embodiment of this application, and FIG. 6 is a third schematic diagram of levels of signals according to an embodiment of this application.
FIG. 5 is a diagram of a time sequence of levels of corresponding signals in a low-frequency display area and a first schematic diagram of initialized voltages generated when an electronic device refreshes an image. As shown in FIG. 5, when the electronic device refreshes the image, if the transistors T1, T4, and T2 are enabled, a DDIC of the electronic device may control the first initialized voltage Vinit1 to be V1, and control the third initialized voltage Vinit3 to be V2.
FIG. 6 is a diagram of a time sequence of levels of corresponding signals in a high-frequency display area and a schematic diagram of initialized voltages generated when an electronic device refreshes an image. As shown in FIG. 6, when the electronic device refreshes the image, if the transistors T1, T4, and T2 are enabled, a DDIC of the electronic device may control the first initialized voltage Vinit1 to be V3, and control the third initialized voltage Vinit3 to be V4. $V 1 > V 3$ and $V 2 < V 4 .$
Optionally, V1 may be equal to V3.
Optionally, V2 may be equal to V4.
If V1>V3 and V2≤V4, and the transistors T1, T4, and T2 in the low-frequency display area are enabled, when the electronic device refreshes a frame of image, in the reset phase, a voltage V1 is written into the capacitor C1, so that a potential of C1 is reset and initialized, a voltage at the N1 point is V1, a voltage at the N2 point is V2, and a voltage difference between the gate and the source of the transistor T3 is a voltage difference between V1 and V2.
In the writing phase, when the transistor T4 is conducted, Vdata is loaded to the N2 point, and the capacitor C1 is charged. In the writing phase, duration in which the second scanning signal remains at a low level is fixed, and duration in which the transistor T4 remains in a conducted state is fixed. Electricity charged to the capacitor C1 in the writing phase is related to a transient characteristic of the transistor T3, or a value of Vdata written into the capacitor C1 in the writing phase is related to the transient characteristic of the transistor T3. The transient characteristic of the transistor T3 is determined by a voltage difference Vgs-1 between the gate and the source of the transistor T3 in the reset phase, that is, determined by the voltage difference between V1 and V2. For example, Vth of the transistor T3 is affected by the voltage difference between the gate and the source of the transistor T3. A more positive voltage difference between the gate and the source of the transistor T3 indicates more positive Vth of the transistor T3, and a more negative voltage difference between the gate and the source of the transistor T3 indicates more negative Vth of the transistor T3.
If V1>V3 and V2≤V4, and the transistors T1, T4, and T2 in the high-frequency display area are enabled, when the electronic device refreshes a frame of image, in the reset phase, a voltage V3 is written into the capacitor C1, so that a potential of C1 is reset and initialized, a voltage at the N1 point is V3, a voltage at the N2 point is V4, and a voltage difference between the gate and the source of the transistor T3 is a voltage difference between V3 and V4.
In the writing phase, when the transistor T4 is conducted, Vdata is loaded to the N2 point, and the capacitor C1 is charged. Similarly, when duration in which the transistor T4 remains in a conducted state is fixed, electricity charged to the capacitor C1 in the writing phase is related to a transient characteristic of the transistor T3, or a value of Vdata written into the capacitor C1 in the writing phase is related to the transient characteristic of the transistor T3. The transient characteristic of the transistor T3 is determined by a voltage difference Vgs-h between the gate and the source of the transistor T3 in the reset phase, that is, determined by the voltage difference between V3 and V4.
When the capacitor C1 is charged in the writing phase, if a voltage difference between the gate and the source of the transistor T3 is larger, Vth of the transistor T3 shifts positively, a current flowing through the transistor T3 is larger, and more electricity is charged to the capacitor C1, or more sufficient Vdata is written into C1. Correspondingly, when the capacitor C1 is charged in the writing phase, if a voltage difference between the gate and the source of the transistor T3 is smaller, Vth of the transistor T3 shifts negatively, a current flowing through the transistor T3 is smaller, and less electricity is charged to the capacitor C1, or more insufficient Vdata is written into C1.
Because Vgs-1>Vgs-h, electricity charged to the capacitor C1 when the transistors T1, T4, and T2 in the low-frequency display area are enabled is more than electricity charged to the capacitor C1 when the transistors T1, T4, and T2 in the high-frequency display area are enabled, or Vdata written into the capacitor C1 when the transistors T1, T4, and T2 in the low-frequency display area are enabled is more sufficient than Vdata written into the capacitor C1 when the transistors T1, T4, and T2 in the high-frequency display area are enabled.
In this way, when the electronic device refreshes an image, electricity each time charged to the capacitor C1 corresponding to the low-frequency display area is increased, which can reduce a difference that is between a gate voltage of the transistor T3 corresponding to the low-frequency display area and a gate voltage of the transistor T3 corresponding to the high-frequency display area and that is generated when the light-emitting element emits light.
In addition, for the low-frequency display area, because the transient characteristic of the transistor T3 is affected by the voltage difference between the gate and the source of the transistor T3, in a process in which the electronic device refreshes 120 frames of images (F1-F120 shown in FIG. 4B and FIG. 4C) in one second, a change generated in display brightness of a corresponding image when the transistors T1, T4, and T2 are enabled and when the transistors T1, T4, and T2 are disabled is as follows:
When F1 is displayed, the corresponding transistors T1, T4, and T2 are enabled, and when F2-F12 are displayed, the corresponding transistors T1, T4, and T2 are disabled, and display brightness of F1-F12 is increasingly bright.
Compared with that the transistors T1, T4, and T2 corresponding to F13 are enabled when F12 and F13 are displayed, display brightness of F13 and brightness of F1 are equivalent to each other, and both are lower than display brightness of F12. When F14-F24 are displayed, the corresponding transistors T1, T4, and T2 are disabled, and display brightness of F13-F24 is increasingly bright.
Similarly, display brightness of F25-F36 is increasingly bright, ..., and display brightness of F109-F120 is increasingly bright.
Due to a change in the voltage difference between the gate and the source of the transistor T3 and in the transient characteristic of the transistor T3, a blinking phenomenon occurs due to an excessively large brightness difference between two adjacent frames of images during display of F1-F120. For example, an excessively large difference between display brightness of F1 and display brightness of F2 leads to blinking, or an excessively large difference between display brightness of F3 and display brightness of F4 leads to blinking, or an excessively large difference between display brightness of F12 and display brightness of F13 leads to a blinking phenomenon.
When an image is displayed in the low-frequency display area, a blinking phenomenon may occur in the low-frequency display area because a relatively large difference exists between brightness of two adjacent frames of images.
Therefore, when the electronic device refreshes an image, increasing electricity each time charged to the capacitor C1 corresponding to the low-frequency display area can further reduce a brightness difference between two adjacent frames of images displayed in the low-frequency display area.
Similarly, if V1≥V3 and V2<V4, and the transistors T1, T4, and T2 are enabled, when the electronic device refreshes a frame of image, because V2<V4, electricity charged to the capacitor C1 corresponding to the low-frequency display area in the reset phase is more than electricity charged to the capacitor C1 corresponding to the high-frequency display area in the reset phase, or Vdata written into the capacitor C1 when the transistors T1, T4, and T2 in the low-frequency display area are enabled is more sufficient than Vdata written into the capacitor C1 when the transistors T1, T4, and T2 in the high-frequency display area are enabled.
In this way, when the electronic device refreshes an image, electricity each time charged to the capacitor C1 corresponding to the low-frequency display area is also improved, which can reduce a difference that is between a gate voltage of the transistor T3 corresponding to the low-frequency display area and a gate voltage of the transistor T3 corresponding to the high-frequency display area and that is generated when the light-emitting element emits light. In addition, increasing electricity each time charged to the capacitor C1 corresponding to the low-frequency display area can further reduce a brightness difference between two adjacent frames of images displayed in the low-frequency display area.
A brightness difference between the high-frequency display area and the low-frequency display area is reduced, and a brightness difference between two adjacent frames of images displayed in the low-frequency display area is reduced, so that in-panel display of the display panel of the electronic device can be more even, thereby improving use experience of using the display surface of electronic device by a user.
Optionally, as shown in FIG. 5 and FIG. 6, when the electronic device is display a frame of image, if the transistors T1, T4, and T2 are disabled, and the capacitor C1 is not charged, the DDIC of the electronic device may control the first initialized voltage Vinit1 to be V3, and control the third initialized voltage Vinit3 to be V4. In this way, power consumption of the electronic device can be reduced.
When the electronic device refreshes each frame of image, a voltage difference between the N1 point and the N2 point in the reset phase is also referred to as a bias voltage of the transistor T3. It may be learned from the foregoing that the bias voltage affects electricity charged to the capacitor C1 in the writing phase.
FIG. 7 is a first diagram of a time sequence of a bias voltage generated when an electronic device refreshes an image, and FIG. 8 is a second diagram of a time sequence of a bias voltage generated when an electronic device refreshes an image. As shown in FIG. 7 and FIG. 8, a first area may be a low-frequency display area, a refresh rate of the first area may be, for example, 10 Hz; and a second area may be a high-frequency display area, and a refresh rate of the second area may be, for example, 120 Hz.
Time for the electronic device to refresh a frame of image based on a row is from 0 to t3. As shown in FIG. 7, in a time period 0-t1, the electronic device drives to display the first area of the frame of image, in a time period t1-t2, the electronic device drives to display the second area of the frame of image, and in a time period t2-t3, the electronic device drives to display the first area of the frame of image. As shown in FIG. 8, in a time period 0-t1, the electronic device drives to display the first area of the frame of image, and in a time period t1-t3, the electronic device drives to display the second area of the frame of image.
As shown in FIG. 5, FIG. 6, FIG. 7, and FIG. 8, when the electronic device refreshes a first frame of image such as F1, the transistors T1, T4, and T2 corresponding to the first area and the second area of F1 are all enabled. The DDIC may control the first initialized voltage Vinit1 and the third initialized voltage Vinit3, to make a bias voltage generated when the first area of F1 is driven to be displayed greater than a bias voltage generated when the second area of F1 is driven to be displayed.
An implementation principle in which the DDIC controls the first initialized voltage Vinit1 and the third initialized voltage Vinit3, to make the bias voltage generated when the first area of F1 is driven to be displayed greater than the bias voltage generated when the second area of F1 is driven to be displayed is similar to an implementation principle of the embodiments shown in FIG. 5 and FIG. 6. Details are not described again.
When the electronic device refreshes a second frame of image such as F2, the transistors T1, T4, and T2 corresponding to the first area of F2 are disabled, and the transistors T1, T4, and T2 corresponding to the second area of F2 are enabled. The DDIC may control the first initialized voltage Vinit1 and the third initialized voltage Vinit3, to make a bias voltage generated when the first area of F2 is driven to be displayed equal to a bias voltage generated when the second area of F2 is driven to be displayed.
Similarly, when the electronic device refreshes a third frame of image such as F3, the transistors T1, T4, and T2 corresponding to the first area of F3 are disabled, and the transistors T1, T4, and T2 corresponding to the second area of F3 are enabled. The DDIC may control the first initialized voltage Vinit1 and the third initialized voltage Vinit3, to make a bias voltage generated when the first area of F3 is driven to be displayed equal to a bias voltage generated when the second area of F3 is driven to be displayed.
Similarly, when the electronic device refreshes a thirteenth frame of image such as F13, the transistors T1, T4, and T2 corresponding to the first area and the second area of F13 are all enabled. The DDIC may control the first initialized voltage Vinit1 and the third initialized voltage Vinit3, to make a bias voltage generated when the first area of F13 is driven to be displayed greater than a bias voltage generated when the second area of F13 is driven to be displayed.
Similarly, when the electronic device refreshes a fourteenth frame of image such as F14, the transistors T1, T4, and T2 corresponding to the first area of F14 are disabled, and the transistors T1, T4, and T2 corresponding to the second area of F14 are enabled. The DDIC may control the first initialized voltage Vinit1 and the third initialized voltage Vinit3, to make a bias voltage generated when the first area of F14 is driven to be displayed equal to a bias voltage generated when the second area of the F14 is driven to be displayed.
In this way, a difference that is between a gate voltage of the transistor T3 corresponding to the low-frequency display area and a gate voltage of the transistor T3 corresponding to the high-frequency display area and that is generated when the light-emitting element emits light can be reduced, to reduce a difference between brightness of the first area and brightness of the second area, and reduce a probability that the first area blinks when the refresh rate of the first area is switched, and/or reduce a probability that the second area blinks when the refresh rate of the second area is switched, thereby reducing a probability that a display panel of the electronic device blinks. In addition, brightness uniformity of the first area may be further improved, to reduce a probability that the first area blinks due to a brightness difference between two adjacent frames of images, and further reduce a probability that the display panel of the electronic device blinks.
The refresh rate of the first area is switched, for example, the refresh rate of the first area is switched to the refresh rate of the second area.
The refresh rate of the second area is switched, for example, the refresh rate of the second area is switched to the refresh rate of the first area.
In a possible implementation, FIG. 9 is a diagram of a time sequence of levels of corresponding signals in a low-frequency display area and a second schematic diagram of initialized voltages generated when an electronic device refreshes an image, FIG. 10 is a third diagram of a time sequence of a bias voltage generated when an electronic device refreshes an image, and FIG. 11 is a fourth diagram of a time sequence of a bias voltage generated when an electronic device refreshes an image. As shown in FIG. 10 and FIG. 11, a first area may be a low-frequency display area, and a refresh rate of the first area is, for example, 10 Hz; and a second area may be a high-frequency display area, and a refresh rate of the second area is, for example, 120 Hz. A diagram of a time sequence of levels of corresponding signals in the high-frequency display area (or the second area) and a schematic diagram of initialized voltages generated when an electronic device refreshes an image are shown in FIG. 6.
Time for the electronic device to refresh a frame of image based on a row is from 0 to t3. As shown in FIG. 10, in a time period 0-t1, the electronic device drives to display the first area of the frame of image, and in a time period t1-t2, the electronic device drives to display the second area of the frame of image, and in a time period t2-t3, the electronic device drives to display the first area of the frame of image. As shown in FIG. 11, in a time period 0-t1, the electronic device drives to display the first area of the frame of image, and in a time period t1-t3, the electronic device drives to display the second area of the frame of image.
As shown in FIG. 6, FIG. 9, FIG. 10, and FIG. 11, when the electronic device refreshes a first frame of image such as F1, the transistors T1, T4, and T2 corresponding to the first area and the second area of F1 are all enabled. The DDIC may control the first initialized voltage Vinit1 and the third initialized voltage Vinit3, to make a bias voltage generated when the first area of F1 is driven to be displayed greater than a bias voltage generated when the second area of F1 is driven to be displayed.
An implementation principle in which the DDIC controls the first initialized voltage Vinit1 and the third initialized voltage Vinit3, to make the bias voltage generated when the first area of F1 is driven to be displayed greater than the bias voltage generated when the second area of F1 is driven to be displayed is similar to an implementation principle of the embodiments shown in FIG. 5 and FIG. 6. Details are not described again.
When the electronic device refreshes a second frame of image such as F2, the transistors T1, T4, and T2 corresponding to the first area of F2 are disabled, and the transistors T1, T4, and T2 corresponding to the second area of F2 are enabled. The DDIC may control the first initialized voltage Vinit1 and the third initialized voltage Vinit3, to make a bias voltage generated when the first area of F2 is driven to be displayed greater than a bias voltage generated when the second area of F2 is driven to be displayed.
Similarly, when the electronic device refreshes a third frame of image such as F3, the transistors T1, T4, and T2 corresponding to the first area of F3 are disabled, and the transistors T1, T4, and T2 corresponding to the second area of F3 are enabled. The DDIC may control the first initialized voltage Vinit1 and the third initialized voltage Vinit3, to make a bias voltage generated when the first area of F3 is driven to be displayed equal to a bias voltage generated when the second area of F3 is driven to be displayed.
Similarly, when the electronic device refreshes a fourth frame of image such as F4, the transistors T1, T4, and T2 corresponding to the first area of F4 are disabled, and the transistors T1, T4, and T2 corresponding to the second area of F4 are enabled. The DDIC may control the first initialized voltage Vinit1 and the third initialized voltage Vinit3, to make a bias voltage generated when the first area of F4 is driven to be displayed equal to a bias voltage generated when the second area of F4 is driven to be displayed.
Similar to the case occurred when the electronic device refreshes the first frame of image such as F1, when the electronic device refreshes a thirteenth frame of image such as F13, the transistors T1, T4, and T2 corresponding to the first area and the second area of F13 are all enabled. The DDIC may control the first initialized voltage Vinit1 and the third initialized voltage Vinit3, to make a bias voltage generated when the first area of F13 is driven to be displayed greater than a bias voltage generated when the second area of F13 is driven to be displayed.
Similar to the case occurred when the electronic device refreshes the second frame of image such as F2, when the electronic device refreshes a fourteenth frame of image such as F14, the transistors T1, T4, and T2 corresponding to the first area of F14 are disabled, and the transistors T1, T4, and T2 corresponding to the second area of F14 are enabled. The DDIC may control the first initialized voltage Vinit1 and the third initialized voltage Vinit3, to make a bias voltage generated when the first area of F14 is driven to be displayed greater than a bias voltage generated when the second area of F14 is driven to be displayed.
Similar to the case occurred when the electronic device refreshes the third frame of image such as F3, when the electronic device refreshes a fifteenth frame of image such as F15, the transistors T1, T4, and T2 corresponding to the first area of F15 are disabled, and the transistors T1, T4, and T2 corresponding to the second area of F15 are enabled. The DDIC may control the first initialized voltage Vinit1 and the third initialized voltage Vinit3, to make a bias voltage generated when the first area of F15 is driven to be displayed equal to a bias voltage generated when the second area of F15 is driven to be displayed.
In this way, a difference that is between a gate voltage of the transistor T3 corresponding to the low-frequency display area and a gate voltage of the transistor T3 corresponding to the high-frequency display area and that is generated when the light-emitting element emits light can be reduced, to reduce a difference between brightness of the first area and brightness of the second area, and further improve brightness uniformity of the first area. It is verified by a test that the voltage control method provided in the embodiments can reduce a probability that a display panel of the electronic device blinks.
In a possible implementation, FIG. 12 is a diagram of a time sequence of levels of corresponding signals in a low-frequency display area and a third schematic diagram of initialized voltages generated when an electronic device refreshes an image, FIG. 13 is a fifth diagram of a time sequence of a bias voltage generated when an electronic device refreshes an image, and FIG. 14 is a sixth diagram of a time sequence of a bias voltage generated when an electronic device refreshes an image. As shown in FIG. 13 and FIG. 14, a first area may be a low-frequency display area, and a refresh rate of the first area is, for example, 10 Hz; and a second area may be a high-frequency display area, and a refresh rate of the second area is, for example, 120 Hz. A diagram of a time sequence of levels of corresponding signals in the high-frequency display area (or the second area) and a schematic diagram of initialized voltages generated when an electronic device refreshes an image are shown in FIG. 6.
Time for the electronic device to refresh a frame of image based on a row is from 0 to t3. As shown in FIG. 13, in a time period 0-t1, the electronic device drives to display the first area of the frame of image, in a time period t1-t2, the electronic device drives to display the second area of the frame of image, and in a time period t2-t3, the electronic device drives to display the first area of the frame of image. As shown in FIG. 14, in a time period 0-t1, the electronic device drives to display the first area of the frame of image, and in a time period t1-t3, the electronic device drives to display the second area of the frame of image.
As shown in FIG. 6, FIG. 12, FIG. 13, and FIG. 14, when the electronic device refreshes a first frame of image such as F1, the transistors T1, T4, and T2 corresponding to the first area and the second area of F1 are all enabled. The DDIC may control the first initialized voltage Vinit1 and the third initialized voltage Vinit3, to make a bias voltage generated when the first area of F1 is driven to be displayed greater than a bias voltage generated when the second area of F1 is driven to be displayed.
An implementation principle in which the DDIC controls the first initialized voltage Vinit1 and the third initialized voltage Vinit3, to make the bias voltage generated when the first area of F1 is driven to be displayed greater than the bias voltage generated when the second area of F1 is driven to be displayed is similar to an implementation principle of the embodiments shown in FIG. 5 and FIG. 6. Details are not described again.
When the electronic device refreshes a second frame of image such as F2, the transistors T1, T4, and T2 corresponding to the first area of F2 are disabled, and the transistors T1, T4, and T2 corresponding to the second area of F2 are enabled. The DDIC may control the first initialized voltage Vinit1 and the third initialized voltage Vinit3, to make a bias voltage generated when the first area of F2 is driven to be displayed greater than a bias voltage generated when the second area of F2 is driven to be displayed.
When the electronic device refreshes a third frame of image such as F3, the transistors T1, T4, and T2 corresponding to the first area of F3 are disabled, and the transistors T1, T4, and T2 corresponding to the second area of F3 are enabled. The DDIC may control the first initialized voltage Vinit1 and the third initialized voltage Vinit3, to make a bias voltage generated when the first area of F3 is driven to be displayed greater than a bias voltage generated when the second area of F3 is driven to be displayed.
When the electronic device refreshes a fourth frame of image such as F4, the transistors T1, T4, and T2 corresponding to the first area of F4 are disabled, and the transistors T1, T4, and T2 corresponding to the second area of F4 are enabled. The DDIC may control the first initialized voltage Vinit1 and the third initialized voltage Vinit3, to make a bias voltage generated when the first area of F4 is driven to be displayed equal to a bias voltage generated when the second area of F4 is driven to be displayed.
When the electronic device refreshes a fifth frame of image such as F5, the transistors T1, T4, and T2 corresponding to the first area of F5 are disabled, and the transistors T1, T4, and T2 corresponding to the second area of F5 are enabled. The DDIC may control the first initialized voltage Vinit1 and the third initialized voltage Vinit3, to make a bias voltage generated when the first area of F5 is driven to be displayed equal to a bias voltage generated when the second area of F5 is driven to be displayed.
A manner and effect of controlling a bias voltage in the first area when the electronic device refreshes a thirteenth frame of image such as F13 is similar to a manner and effect of controlling a bias voltage in the first area when the electronic device refreshes the first frame of image such as F1. A manner and effect of controlling a bias voltage in the first area when the electronic device refreshes a fourteenth frame of image such as F14 is similar to a manner and effect of controlling a bias voltage in the first area when the electronic device refreshes the second frame of image such as F2. A manner and effect of controlling a bias voltage in the first area when the electronic device refreshes a fifteenth frame of image such as F15 is similar to a manner and effect of controlling a bias voltage in the first area when the electronic device refreshes the third frame of image such as F3. A manner and effect of controlling a bias voltage in the first area when the electronic device refreshes a sixteenth frame of image such as F16 is similar to a manner and effect of controlling a bias voltage in the first area when the electronic device refreshes the fourth frame of image such as F4. Details are not described again.
In this way, a difference that is between a gate voltage of the transistor T3 corresponding to a still image display area and a gate voltage of the transistor T3 corresponding to a dynamic image display area and that is generated when the light-emitting element emits light can be reduced, to reduce a difference between brightness of the first area and brightness of the second area, and further improve brightness uniformity of the first area. It is verified by a test that the voltage control method provided in the embodiments can reduce a probability that a display panel of the electronic device blinks.
The following further describes the voltage control method provided in the embodiments of this application with reference to FIG. 15, FIG. 4A to FIG. 4C, FIG. 5, FIG. 6, FIG. 7, FIG. 8, FIG. 9, FIG. 10, FIG. 11, FIG. 12, FIG. 13, and FIG. 14.
FIG. 15 is a second schematic diagram of a pixel circuit according to an embodiment of this application. As shown in FIG. 15, the pixel circuit includes:

a drive module 13, where a control end of the drive module 13 is connected to a first node N1, and a source end of the drive module 13 is connected to a second node N2; the drive module 13 may include a driving thin film transistor (DTFT); a drain end of the DTFT is connected to a third node N3, and the DTFT is configured to output a current to the third node N3 under control of the first node N1; and the DTFT may include the transistor T3 shown in FIG. 2;
a first reset unit 10, connected to the first node N1, and configured to load a first initialized voltage to the shown first node N1 in response to a first reset signal, where the first reset unit 10 may include a first reset transistor, and the first reset transistor is the transistor T1 shown in FIG. 2;
a storage capacitor 11, where one end is connected to the first node N1, and the other end is connected to a power supply positive electrode (VDD); and the storage capacitor 11 may include the capacitor C1 shown in FIG. 2;
a first light-emitting control unit 12, connected to the power supply positive electrode and the second node N2, and configured to load a first power supply voltage of the power supply positive electrode to the second node N2 in response to a light-emitting control signal, where the first light-emitting control unit 12 may include a first light-emitting control transistor, and the first light-emitting control transistor is the transistor T5 shown in FIG. 2;
a threshold compensation unit 14, connected to the first node N1 and the third node N3, and configured to conduct the third node N3 and the first node N1 in response to a first scanning signal, where the threshold compensation unit 14 may include a threshold compensation transistor, and the threshold compensation transistor is the transistor T2 shown in FIG. 2;
a second light-emitting control unit 15, connected to the third node N3 and a fourth node N4, and configured to conduct the third node N3 and the fourth node N4 in response to a light-emitting control signal, where the second light-emitting control unit 15 may include a second light-emitting control transistor, and the second light-emitting control transistor is the transistor T6 shown in FIG. 2;
a light-emitting element 16, where one end is connected to the fourth node, and the other end is connected to a power supply negative electrode to load a second power supply voltage of the power supply negative electrode; and the light-emitting element 16 may include an organic light-emitting diode (OLED);
a second reset unit 17, connected to the fourth node N4, and configured to load a second initialized voltage to the fourth node N4 in response to a second reset signal, where the second reset unit 17 may include a second reset transistor, and the second reset transistor is the transistor T7 shown in FIG. 2; and
a data writing unit 18, connected to the second node N2, and configured to load a data voltage to the second node N2 in response to a second scanning signal, where the data writing unit 18 may include a data writing transistor, and the data writing transistor is the transistor T4 shown in FIG. 2.

That the first reset unit 10 is conducted may be referred to as that the first reset unit 10 is enabled. That the first reset unit 10 is not conducted may be referred to as that the first reset unit 10 is disabled. That the data writing unit 18 loads the data voltage to the second node N2 in response to the second scanning signal may be referred to as that the data writing unit 18 is enabled. That the data writing unit 18 does not load the data voltage to the second node N2 may be referred to as that the data writing unit 18 is disabled. That the threshold compensation unit 14 conducts the third node N3 and the first node N1 in response to the first scanning signal may be referred to as that the threshold compensation unit 14 is enabled. That the threshold compensation unit 14 does not conduct the third node N3 to the first node N1 may be referred to as that the threshold compensation unit 14 is disabled.
A third reset unit 19 is connected to the second node N2, and is configured to load a third initialized voltage to the second node N2 in response to the second reset signal, where the third reset unit 19 may include a third reset transistor, and the third reset transistor is the transistor T8 shown in FIG. 2.
As shown in FIG. 4A to FIG. 4C, FIG. 5, FIG. 6, FIG. 7, and FIG. 8, when driving to display a first area of a first frame of image, the electronic device controls a voltage of the first node to be a first voltage, and controls a voltage of the second node to be a second voltage. The first voltage may include V1. The second voltage may include V2.
When driving to display a second area of the first frame of image, the electronic device controls the voltage of the first node to be a third voltage, and controls the voltage of the second node to be a fourth voltage. The third voltage may include V3. The fourth voltage may include V4.
A voltage difference between the first voltage and the second voltage is greater than a voltage difference between the third voltage and the fourth voltage; and a refresh rate of the first area is a first refresh rate, a refresh rate of the second area is a second refresh rate, and the first refresh rate is less than the second refresh rate. The first refresh rate is, for example, 10 Hz. The second refresh rate is, for example, 120 Hz.
Optionally, the first voltage is greater than the third voltage, and/or the second voltage is less than the fourth voltage.
Further, as shown in FIG. 15, the pixel circuit further includes the data writing unit 18, and the data writing unit 18 is connected to the second node N2. As shown in FIG. 3 and FIG. 4A to FIG. 4C, when the electronic device displays either the first area or the second area of the first frame of image, the data writing unit 18 is enabled. The voltage control method provided in the embodiments further includes the following:
As shown in FIG. 5, when driving to display the first area of a second frame of image, the electronic device controls the voltage of the first node to be the third voltage, and controls the voltage of the second node to be the fourth voltage. When the electronic device displays the first area of the second frame of image, the data writing unit 18 is disabled.
As shown in FIG. 6, when driving to display the second area of the second frame of image, the electronic device controls the voltage of the first node to be the third voltage, and controls the voltage of the second node to be the fourth voltage. When the electronic device displays the second area of the second frame of image, the data writing unit 18 is enabled.
Optionally, as shown in FIG. 15, the pixel circuit further includes the data writing unit 18 and the threshold compensation unit 14. As shown in FIG. 3 and FIG. 4A to FIG. 4C, when the electronic device displays either the first area or the second area of the first frame of image, the first reset unit 10 is enabled, the data writing unit 18 is enabled, and the threshold compensation unit 14 is enabled. The voltage control method provided in the embodiments further includes the following:
As shown in FIG. 5, when driving to display the first area of a second frame of image, the electronic device controls the voltage of the first node to be the third voltage, and controls the voltage of the second node to be the fourth voltage. When the electronic device displays the first area of the second frame of image, the first reset unit 10, the data writing unit 18, and the threshold compensation unit 14 are disabled.
As shown in FIG. 6, when driving to display the second area of the second frame of image, the electronic device controls the voltage of the first node to be the third voltage, and controls the voltage of the second node to be the fourth voltage. When the electronic device displays the second area of the second frame of image, the first reset unit 10, the data writing unit 18, and the threshold compensation unit 14 are enabled.
Optionally, a display area on a display panel of the electronic device may further include a third area. When driving to display the third area of the first frame of image, the electronic device controls the voltage of the first node to be the first voltage, and controls the voltage of the second node to be the second voltage. A refresh rate of the third area is a third refresh rate. The third refresh rate is less than the second refresh rate.
Optionally, the third refresh rate may be the same as the first refresh rate, or the third refresh rate may be different from the first refresh rate. When the third refresh rate is the same as the first refresh rate, the third area is, for example, the first area corresponding to the time period t2-t3 shown in FIG. 7, FIG. 10, and FIG. 13.
It may be understood that both the first refresh rate and the third refresh rate in this embodiment of this application may include but are not limited to 10 Hz. The second refresh rate in this embodiment of this application includes but is not limited to 120 Hz. For example, the third refresh rate may be 30 Hz, 60 Hz, or the like.
Optionally, when refreshing a frame of image, the electronic device may determine a start position and an end position of the first area based on an identifier of the pixel circuit corresponding to the first area, and determine a start position and an end position of the second area based on an identifier of the pixel circuit corresponding to the second area.
For example, the DDIC may determine the start position and the end position of the second area by using position information that is of the second area and that is indicated by an application processor (AP) of the electronic device, so as to determine the start position and the end position of the first area. The position information that is of the second area and that is indicated by the AP may be relative position information that is of the second area and that is indicated by the AP, or may be real position information that is of the second area and that is indicated by the AP. The real position information that is of the second area and that is indicated by the AP may include an identifier of the pixel circuit corresponding to the start position of the second area and an identifier of the pixel circuit corresponding to the end position.
The position information that is of the second area and that is indicated by the AP is determined by the AP based on an application type to which image data generated by the AP belongs or based on an application scenario to which the image data generated by the AP belongs. The image data generated by the AP refers to data corresponding to Vdata when the transistors T4 and T2 are enabled. If the image data generated by the AP is dynamic image data of an application A, the position information that is of the second area and that is indicated by the AP may be determined based on position information of an area in which a dynamic image is displayed in a display interface of the application A.
Specific implementation principles and technical effects of this embodiment are similar to specific implementation principles and technical effects of the embodiments shown in FIG. 2, FIG. 5, FIG. 6, FIG. 7, and FIG. 8. Details are not described again.
As shown in FIG. 15, FIG. 4 A to FIG. 4C, FIG. 6, FIG. 9, FIG. 10, and FIG. 11, when the electronic device displays either the first area or the second area of the first frame of image, the data writing unit 18 is enabled. The voltage control method provided in the embodiments further includes the following:
When driving to display the first area of a second frame of image, the electronic device controls the voltage of the first node to be the first voltage, and controls the voltage of the second node to be the second voltage. When the electronic device displays the first area of the second frame of image, the data writing unit 18 is disabled.
When driving to display the second area of the second frame of image, the electronic device controls the voltage of the first node to be the third voltage, and controls the voltage of the second node to be the fourth voltage. When the electronic device displays the first area of the second frame of image, the data writing unit 18 is enabled.
Specific implementation principles and technical effects of this embodiment are similar to specific implementation principles and technical effects of the embodiments shown in FIG. 6, FIG. 9, FIG. 10, and FIG. 11. Details are not described again.
For example, as shown in FIG. 15, FIG. 4 A to FIG. 4C, FIG. 6, FIG. 9, FIG. 10, and FIG. 11, when the electronic device displays either the first area or the second area of the first frame of image, the first reset unit 10 is enabled, the data writing unit 18 is enabled, and the threshold compensation unit 14 is enabled. The voltage control method provided in the embodiments further includes the following:
When driving to display the first area of a second frame of image, the electronic device controls the voltage of the first node to be the first voltage, and controls the voltage of the second node to be the second voltage. When the electronic device displays the first area of the second frame of image, the first reset unit 10, the data writing unit 18, and the threshold compensation unit 14 are disabled.
When driving to display the second area of the second frame of image, the electronic device controls the voltage of the first node to be the third voltage, and controls the voltage of the second node to be the fourth voltage. When the electronic device displays the first area of the second frame of image, the first reset unit 10, the data writing unit 18, and the threshold compensation unit 14 are enabled.
Specific implementation principles and technical effects of this embodiment are similar to specific implementation principles and technical effects of the embodiments shown in FIG. 6, FIG. 9, FIG. 10, and FIG. 11. Details are not described again.
As shown in FIG. 15, FIG. 4 A to FIG. 4C, FIG. 6, FIG. 12, FIG. 13, and FIG. 14, the voltage control method provided in the embodiments further includes the following:
When driving to display the first area of a third frame of image, the electronic device controls the voltage of the first node to be the first voltage, and controls the voltage of the second node to be the second voltage. When the electronic device displays the first area of the third frame of image, the data writing unit 18 is disabled.
When driving to display the second area of the third frame of image, the electronic device controls the voltage of the first node to be the third voltage, and controls the voltage of the second node to be the fourth voltage. When the electronic device displays the second area of the third frame of image, the data writing unit 18 is enabled.
When driving to display the first area of a fourth frame of image, the electronic device controls the voltage of the first node to be the third voltage, and controls the voltage of the second node to be the fourth voltage. When the electronic device displays the first area of the fourth frame of image, the data writing unit 18 is disabled.
When driving to display the second area of the fourth frame of image, the electronic device controls the voltage of the first node to be the third voltage, and controls the voltage of the second node to be the fourth voltage. When the electronic device displays the second area of the fourth frame of image, the data writing unit 18 is enabled.
Specific implementation principles and technical effects of this embodiment are similar to specific implementation principles and technical effects of the embodiments shown in FIG. 6, FIG. 12, FIG. 13, and FIG. 14. Details are not described again.
For example, as shown in FIG. 15, FIG. 4 A to FIG. 4C, FIG. 6, FIG. 12, FIG. 13, and FIG. 14, the voltage control method provided in the embodiments further includes the following:
When driving to display the first area of a third frame of image, the electronic device controls the voltage of the first node to be the first voltage, and controls the voltage of the second node to be the second voltage. When the electronic device displays the first area of the third frame of image, the first reset unit 10, the data writing unit 18, and the threshold compensation unit 14 are disabled.
When driving to display the second area of the third frame of image, the electronic device controls the voltage of the first node to be the third voltage, and controls the voltage of the second node to be the fourth voltage. When the electronic device displays the second area of the third frame of image, the first reset unit 10, the data writing unit 18, and the threshold compensation unit 14 are enabled.
When driving to display the first area of a fourth frame of image, the electronic device controls the voltage of the first node to be the third voltage, and controls the voltage of the second node to be the fourth voltage. When the electronic device displays the first area of the fourth frame of image, the first reset unit 10, the data writing unit 18, and the threshold compensation unit 14 are disabled.
When driving to display the second area of the fourth frame of image, the electronic device controls the voltage of the first node to be the third voltage, and controls the voltage of the second node to be the fourth voltage. When the electronic device displays the second area of the fourth frame of image, the first reset unit 10, the data writing unit 18, and the threshold compensation unit 14 are enabled.
Specific implementation principles and technical effects of this embodiment are similar to specific implementation principles and technical effects of the embodiments shown in FIG. 6, FIG. 12, FIG. 13, and FIG. 14. Details are not described again.
To better understand the embodiments of this application, the following describes a structure of the electronic device in the embodiments of this application with reference to FIG. 16 and FIG. 17.
FIG. 16 is a schematic diagram of a structure of an electronic device 100.
The electronic device 100 may include a processor 110, an external storage interface 120, an internal storage 121, a universal serial bus (universal serial bus, USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, a headset jack 170D, a sensor module 180, a button 190, a motor 191, an indicator 192, a camera 193, a display screen 194, a subscriber identification module (subscriber identification module, SIM) card interface 195, and the like. The sensor module 180 may include a pressure sensor 180A, a gyroscope sensor 180B, a barometric pressure sensor 180C, a magnetic sensor 180D, an acceleration sensor 180E, a distance sensor 180F, an optical proximity sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, and the like.
It may be understood that the structure shown in this embodiment of the present invention does not constitute a specific limitation on the electronic device 100. In some other embodiments of this application, the electronic device 100 may include more or fewer components than those shown in the figure, combine some components, split some components, or have different component arrangements. The components shown in the figure may be implemented by hardware, software, or a combination of software and hardware.
The processor 110 may include one or more processing units. For example, the processor 110 may include an application processor (application processor, AP), a modem processor, a graphics processing unit (graphics processing unit, GPU), an image signal processor (image signal processor, ISP), a controller, a video codec, a digital signal processor (digital signal processor, DSP), a baseband processor, a neural-network processing unit (neural-network processing unit, NPU), and/or the like. Different processing units may be independent devices, or may be integrated into one or more processors.
The controller may generate an operation control signal based on instruction operation code and a timing signal, to complete control of instruction fetching and instruction execution.
A storage may be further disposed in the processor 110 to store instructions and data. In some embodiments, the storage in the processor 110 is a cache. The storage may store instructions or data recently used or cyclically used by the processor 110. If the processor 110 needs to use the instructions or the data again, the processor 110 may directly invoke the instructions or the data from the storage. This avoids repeated access and reduces waiting time of the processor 110, thereby improving system efficiency.
In some embodiments, the processor 110 may include one or more interfaces. The interface may include an inter-integrated circuit (inter-integrated circuit, I2C) interface, an inter-integrated circuit sound (inter-integrated circuit sound, I2S) interface, a pulse code modulation (pulse code modulation, PCM) interface, a universal asynchronous receiver/transmitter (universal asynchronous receiver/transmitter, UART) interface, a mobile industry processor interface (mobile industry processor interface, MIPI), a general-purpose input/output (general-purpose input/output, GPIO) interface, a subscriber identity module (subscriber identity module, SIM) interface, a universal serial bus (universal serial bus, USB) interface, and/or the like.
It may be understood that an interface connection relationship between modules illustrated in this embodiment of the present invention is merely an example for description, and does not constitute a limitation on the structure of the electronic device 100. In some other embodiments of this application, the electronic device 100 may alternatively use an interface connection manner different from that in the foregoing embodiment, or use a combination of a plurality of interface connection manners.
The charging management module 140 is configured to receive a charging input from a charger. The charger may be a wireless charger or a wired charger. In some embodiments of wired charging, the charging management module 140 may receive a charging input from a wired charger through the USB interface 130. In some embodiments of wireless charging, the charging management module 140 may receive a wireless charging input by using a wireless charging coil of the electronic device 100. When charging the battery 142, the charging management module 140 may further supply power to the electronic device through the power management module 141.
The power management module 141 is configured to connect to the battery 142, the charging management module 140, and the processor 110. The power management module 141 receives an input from the battery 142 and/or an input from the charging management module 140, and supplies power to the processor 110, the internal storage 121, the display screen 194, the camera 193, the wireless communication module 160, and the like. The power management module 141 may be further configured to monitor parameters such as a battery capacity, a quantity of battery cycles, and a battery health status (leakage or impedance). In some other embodiments, the power management module 141 may alternatively be disposed in the processor 110. In some other embodiments, the power management module 141 and the charging management module 140 may alternatively be disposed in a same device.
A wireless communication function of the electronic device 100 may be implemented by using the antenna 1, the antenna 2, the mobile communication module 150, the wireless communication module 160, the modem processor, the baseband processor, and the like shown in FIG. 16.
The antenna 1 and the antenna 2 shown in FIG. 16 are configured to transmit or receive an electromagnetic wave signal. Each antenna in the electronic device 100 may be configured to cover one or more communication frequency bands. Different antennas may be further multiplexed to improve antenna utilization. For example, the antenna 1 may be multiplexed as a diversity antenna of a wireless local area network. In some other embodiments, the antenna may be used together with a tuning switch.
The mobile communication module 150 may provide a solution applied to the electronic device 100 for wireless communication including 2G/3G/4G/5G and the like. The mobile communication module 150 may include at least one filter, switch, power amplifier, low noise amplifier (low noise amplifier, LNA), and the like. The mobile communication module 150 may receive an electromagnetic wave by using the antenna 1, perform processing such as filtering or amplification on the received electromagnetic wave, and transmit a processed electromagnetic wave to the modem processor for demodulation. The mobile communication module 150 may further amplify a signal obtained after modulation by the modem processor, and convert an amplified signal into an electromagnetic wave for radiation through the antenna 1. In some embodiments, at least some functional modules in the mobile communication module 150 may be disposed in the processor 110. In some embodiments, at least some functional modules in the mobile communication module 150 may be disposed in a same device as at least some modules in the processor 110.
The modem processor may include a modulator and a demodulator. The modulator is configured to modulate a to-be-sent low frequency baseband signal into a medium or high frequency signal. The demodulator is configured to demodulate a received electromagnetic wave signal into a low frequency baseband signal. Then, the demodulator transmits, to the baseband processor for processing, the low frequency baseband signal obtained through demodulation. The low frequency baseband signal is processed by the baseband processor and then transmitted to the application processor. The application processor outputs a sound signal by using an audio device (not limited to the speaker 170A, the receiver 170B, and the like), or displays an image or a video by using the display screen 194. In some embodiments, the modem processor may be an independent device. In some other embodiments, the modem processor may be independent of the processor 110 and disposed in a same device as the mobile communication module 150 or another functional module.
The wireless communication module 160 may provide a solution for wireless communication that is applied to the electronic device 100 and that includes a wireless local area network (wireless local area networks, WLAN) (for example, a wireless fidelity (wireless fidelity, Wi-Fi) network), Bluetooth (Bluetooth, BT), a global navigation satellite system (global navigation satellite system, GNSS), frequency modulation (frequency modulation, FM), a near field communication (near field communication, NFC) technology, an infrared (infrared, IR) technology, and the like. The wireless communication module 160 may be one or more devices integrating at least one communication processing module. The wireless communication module 160 receives an electromagnetic wave by using the antenna 2, performs frequency modulation and filtering processing on an electromagnetic wave signal, and sends a processed signal to the processor 110. The wireless communication module 160 may further receive a to-be-sent signal from the processor 110, perform frequency modulation and amplification on the to-be-sent signal, and convert, by using the antenna 2, the to-be-sent signal into an electromagnetic wave for radiation.
In some embodiments, in the electronic device 100, the antenna 1 is coupled to the mobile communication module 150, and the antenna 2 is coupled to the wireless communication module 160, so that the electronic device 100 can communicate with a network and another device by using a wireless communication technology. The wireless communication technology may include a global system for mobile communications (global system for mobile communications, GSM), a general packet radio service (general packet radio service, GPRS), code division multiple access (code division multiple access, CDMA), wideband code division multiple access (wideband code division multiple access, WCDMA), time-division code division multiple access (time-division code division multiple access, TD-SCDMA), long term evolution (long term evolution, LTE), BT, a GNSS, a WLAN, NFC, FM, an IR technology, and/or the like. The GNSS may include a global positioning system (global positioning system, GPS), a global navigation satellite system (global navigation satellite system, GLONASS), a BeiDou navigation satellite system (beidou navigation satellite system, BDS), a quasi-zenith satellite system (quasi-zenith satellite system, QZSS), and/or a satellite based augmentation system (satellite based augmentation systems, SBAS).
The electronic device 100 implements a display function by using the GPU, the display screen 194, the application processor, and the like. The GPU is a microprocessor for image processing, and is connected to the display screen 194 and the application processor. The GPU is configured to perform mathematical and geometric computing for graphics rendering. The processor 110 may include one or more GPUs that execute program instructions to generate or change displayed information.
The display screen 194 is configured to display an image, a video, and the like. The display screen 194 includes a display panel. The display panel may be a liquid crystal display (liquid crystal display, LCD), an organic light-emitting diode (organic light-emitting diode, OLED), an active-matrix organic light emitting diode or active-matrix organic light emitting diode (active-matrix organic light emitting diode, AMOLED), a flexible light-emitting diode (flex light-emitting diode, FLED), a Miniled, a MicroLed, a Micro-oLed, a quantum dot light emitting diode (quantum dot light emitting diodes, QLED), or the like. In some embodiments, the electronic device 100 may include one or N display screens 194, where N is a positive integer greater than 1.
The electronic device 100 may implement a photographing function by using the ISP, the camera 193, the video codec, the GPU, the display screen 194, the application processor, and the like.
The ISP is configured to process data fed back by the camera 193. For example, during photographing, a shutter is opened, and light is transmitted to a photosensitive element of the camera through a lens. An optical signal is converted into an electrical signal. The photosensitive element of the camera transmits the electrical signal to the ISP for processing, to convert the electrical signal into an image visible to naked eyes. The ISP may further perform algorithm optimization on noise, brightness, and complexion of the image. The ISP may further optimize parameters such as exposure and color temperature of a photographing scene. In some embodiments, the ISP may be disposed in the camera 193.
The camera 193 is configured to capture a still image or a video. An optical image of an object is generated through the lens and is projected onto the photosensitive element. The photosensitive element may be a charge coupled device (charge coupled device, CCD) or a complementary metal-oxide-semiconductor (complementary metal-oxide-semiconductor, CMOS) phototransistor. The photosensitive element converts an optical signal into an electrical signal, and then transmits the electrical signal to the ISP to convert the electrical signal into a digital image signal. The ISP outputs the digital image signal to the DSP for processing. The DSP converts the digital image signal into an image signal in a standard format, for example, RGB or YUV. In some embodiments, the electronic device 100 may include one or N cameras 193, where N is a positive integer greater than 1.
The digital signal processor is configured to process a digital signal, and may further process another digital signal in addition to a digital image signal. For example, when the electronic device 100 selects a frequency, the digital signal processor is configured to perform Fourier transform and the like on frequency energy.
The video codec is configured to compress or decompress a digital video. The electronic device 100 may support one or more video codecs. In this way, the electronic device 100 may play or record videos in a plurality of encoding formats, for example, moving picture experts group (moving picture experts group, MPEG) 1, MPEG2, MPEG3, and MPEG4.
The NPU is a neural-network (neural-network, NN) computing processor, which quickly processes input information by referring to a biological neural network structure, for example, by referring to a transmission mode between human brain neurons, and may further perform self-learning continuously. Applications such as intelligent cognition of the electronic device 100, for example, image recognition, face recognition, voice recognition, and text understanding, may be implemented by using the NPU.
The external storage interface 120 may be configured to connect to an external storage card, for example, a Micro SD card, to expand a storage capability of the electronic device 100. The external storage card communicates with the processor 110 through the external storage interface 120, to implement a data storage function. For example, files such as music and videos are stored in the external storage card.
The internal storage 121 may be configured to store computer-executable program code, and the executable program code includes instructions. The internal storage 121 may include a program storage area and a data storage area. The program storage area may store an operating system, an application required by at least one function (for example, a sound playing function or an image playing function), and the like. The data storage area may store data (for example, audio data and a phone book) and the like created during use of the electronic device 100. In addition, the internal storage 121 may include a high-speed random access memory, and may further include a nonvolatile memory, for example, at least one magnetic disk storage device, a flash memory device, or a universal flash storage (universal flash storage, UFS). The processor 110 performs various function applications and data processing of the electronic device 100 by running the instructions stored in the internal storage 121 and/or the instructions stored in the storage disposed in the processor.
The electronic device 100 may implement audio functions, for example, music playing and recording, by using the audio module 170, the speaker 170A, the receiver 170B, the microphone 170C, the headset jack 170D, the application processor, and the like.
The audio module 170 is configured to convert digital audio information into an analog audio signal for output, and is further configured to convert an analog audio input into a digital audio signal. The audio module 170 may be further configured to encode and decode an audio signal. In some embodiments, the audio module 170 may be disposed in the processor 110 or some functional modules of the audio module 170 may be disposed in the processor 110.
The speaker 170A, also referred to as a "loudspeaker", is configured to convert an audio electrical signal into a sound signal. The electronic device 100 may be used to listen to music or answer a call in a hands-free mode by using the speaker 170A.
The receiver 170B, also referred to as an "earpiece", is configured to convert an audio electrical signal into a sound signal. When a call is answered or a voice message is listened to by using the electronic device 100, the receiver 170B may be put close to a human ear to listen to a voice.
The microphone 170C, also referred to as a "mic" or "mike", is configured to convert a sound signal into an electrical signal. When making a call or sending a voice message, a user may make a sound by approaching the mouth to the microphone 170C, to input a sound signal to the microphone 170C. At least one microphone 170C may be disposed in the electronic device 100. In some other embodiments, two microphones 170C may be disposed in the electronic device 100, to implement a noise reduction function in addition to collecting a sound signal. In some other embodiments, three, four, or more microphones 170C may alternatively be disposed in the electronic device 100, to collect a sound signal, reduce noise, further recognize a sound source, implement a directional sound recording function, and so on.
The headset jack 170D is configured to connect to a wired headset. The headset jack 170D may be the USB interface 130, or may be a 3.5 mm open mobile electronic terminal platform (open mobile terminal platform, OMTP) standard interface or a cellular telecommunications industry association of the USA (cellular telecommunications industry association of the USA, CTIA) standard interface.
The button 190 includes a power on/off button, a volume button, or the like. The button 190 may be a mechanical button, or may be a touch button. The electronic device 100 may receive a key input and generate a key signal input related to user settings and function control of the electronic device 100.
The motor 191 may generate a vibration prompt. The motor 191 may be configured to provide a vibration prompt for an incoming call, and may also be configured to provide vibration feedback for a touch. For example, touch operations performed on different applications (for example, photographing and audio playing) may correspond to different vibration feedback effects. The motor 191 may also correspond to different vibration feedback effects for touch operations performed on different areas of the display screen 194. Different application scenarios (for example, a time reminder, information receiving, an alarm clock, and a game) may also correspond to different vibration feedback effects. A touch vibration feedback effect may be further customized.
The indicator 192 may be an indicator light, may be configured to indicate a charging status or a power change, and may be further configured to indicate a message, a missed incoming call, a notification, and the like.
The SIM card interface 195 is configured to connect to a SIM card. The SIM card may be inserted into the SIM card interface 195 or removed from the SIM card interface 195 to implement contact with and separation from the electronic device 100. The electronic device 100 may support one or N SIM card interfaces, where N is a positive integer greater than 1. The SIM card interface 195 may support a Nano SIM card, a Micro SIM card, a SIM card, and the like. A plurality of cards may be simultaneously inserted into a same SIM card interface 195. The plurality of cards may be of a same type or different types. The SIM card interface 195 may be further compatible with SIM cards of different types. The SIM card interface 195 may also be compatible with an external storage card. The electronic device 100 interacts with a network by using the SIM card, to implement functions such as a call and data communication. In some embodiments, the electronic device 100 uses an eSIM, that is, an embedded SIM card. The eSIM card may be embedded in the electronic device 100 and cannot be separated from the electronic device 100.
A software system of the electronic device 100 may use a layered architecture, an event-driven architecture, a microkernel architecture, a microservice architecture, or a cloud architecture. In the embodiments of the present invention, an Android system with a layered architecture is used as an example to describe a software structure of the electronic device 100.
FIG. 17 is a block diagram of a software structure of an electronic device 100 according to an embodiment of the present invention.
In the layered architecture, software is divided into several layers, and each layer has a clear role and task. The layers communicate with each other through software interfaces. In some embodiments, the Android system is divided into four layers from top to bottom: an application layer, an application framework layer, an Android runtime (Android runtime) and system library, and a kernel layer.
The application layer may include a series of application packages.
As shown in FIG. 17, the application packages may include applications such as Camera, Gallery, Game, Phone, Map, Navigation, WLAN, Bluetooth, Music, Videos, and Messages.
The application framework layer provides an application programming interface (application programming interface, API) and a programming framework for an application at the application layer. The application framework layer includes some predefined functions.
As shown in FIG. 17, the application framework layer may include a window manager, a content provider, a view system, a phone manager, a resource manager, a notification manager, and the like.
The window manager is configured to manage a window program. The window manager may obtain a size of a display screen, determine whether a status bar exists, lock a screen, take a screenshot, and the like.
The content provider is configured to store and obtain data, and enable the data to be accessible to an application. The data may include a video, an image, audio, calls that are made and answered, a browsing history and bookmarks, a phone book, and the like.
The view system includes visual controls such as a text display control and a picture display control. The view system may be configured to build an application. A display panel may include one or more views. For example, a display panel including an SMS message notification icon may include a view for displaying a text and a view for displaying a picture.
The phone manager is configured to provide the electronic device 100 with a communication function, for example, call status management (including answering, hanging up, and the like).
The resource manager provides various resources for an application, for example, a localized string, an icon, a picture, a layout file, and a video file.
The notification manager enables the application to display notification information in a status bar, and may be configured to convey a notification-type message. The displayed notification information may automatically disappear after a short stay without user interaction. For example, the notification manager is configured to provide a notification of download completion, a message reminder, and the like. The notification manager may alternatively be a notification that appears in a top status bar of the system in a form of a graph or scroll bar text, for example, a notification of an application running in the background or a notification that appears on a screen in a form of a dialog window. For example, text information is prompted in the status bar, an alert sound is made, the electronic device vibrates, or an indicator light blinks.
The Android Runtime includes a kernel library and a virtual machine. The Android runtime is responsible for scheduling and management the Android system.
The kernel library includes two parts: One part is a functional function that needs to be invoked in a java language, and the other part is a kernel library of Android.
The application layer and the application framework layer run in the virtual machine. The virtual machine executes java files at the application layer and the application framework layer as binary files. The virtual machine is configured to perform functions such as object lifecycle management, stack management, thread management, security and exception management, and garbage collection.
The system library may include a plurality of functional modules, for example, a surface manager (surface manager), a media library (Media Libraries), a three-dimensional graphics processing library (for example, OpenGL ES), and a 2D graphics engine (for example, an SGL).
The surface manager is configured to manage a display subsystem, and provide 2D and 3D layer fusion for a plurality of applications.
The media library supports playing and recording in a plurality of common audio and video formats, a still image file, and the like. The media library may support a plurality of audio and video encoding formats, such as MPEG4, H.264, MP3, AAC, AMR, JPG, and PNG.
The three-dimensional graphics processing library is configured to implement three-dimensional graphics drawing, image rendering and composition, layer processing, and the like.
The 2D graphics engine is a drawing engine for 2D graphics drawing.
The kernel layer is a layer between hardware and software. The kernel layer includes at least a display driver, a camera driver, an audio driver, and a sensor driver.
The following describes example working procedures of software and hardware of the electronic device 100 with reference to a capturing and photographing scene.
When the touch sensor 180K receives a touch operation, a corresponding hardware interrupt is sent to the kernel layer. The kernel layer processes the touch operation into an original input event (including information such as touch coordinates and a timestamp of the touch operation). The original input event is stored at the kernel layer. The application framework layer obtains the original input event from the kernel layer, and identifies a control corresponding to the input event. For example, the touch operation is a touch single-tap operation, and a control corresponding to the single-tap operation is a control of a camera application icon. A camera application invokes an interface of the application framework layer to start the camera application, so that the kernel layer is invoked to start the camera driver, and the camera 193 captures a still image or a video.
The voltage control method provided in the embodiment of this application may be applied to an electronic device having a communication function. The electronic device includes a terminal device. For a specific device form and the like of the terminal device, refer to the foregoing related description. Details are not described herein again.
An embodiment of this application provides an electronic device, and the electronic device includes a processor, a display driver integrated circuit (DDIC), a pixel circuit, and a storage. The storage stores computer-executable instructions. The processor indicates the display driver integrated circuit to drive the pixel circuit. The display driver integrated circuit executes computer-executable instructions stored in a storage, to enable the electronic device to perform the foregoing method, and drive the pixel circuit.
An embodiment of this application provides a chip. The chip includes a processor, and the processor is configured to invoke a computer program in a storage to execute the technical solutions in the foregoing embodiments. The implementation is similar to the foregoing related embodiments in terms of implementation principles and technical effects. Details are not described herein again.
An embodiment of this application further provides a computer-readable storage medium. The computer-readable storage medium stores a computer program. The computer program is executed by the display driver integrated circuit (DDIC) to implement the foregoing method. All or some of the methods described in the foregoing embodiments may be implemented by using software, hardware, firmware, or any combination thereof. If implemented in software, functions may be stored in a computer-readable medium or transmitted on a computer-readable medium as one or more instructions or code. The computer-readable medium may include a computer storage medium and a communication medium, and may further include any medium that enables a computer program to be transmitted from a place to another place. The storage medium may be any target medium accessible by a computer.
In a possible implementation, the computer-readable medium may include a RAM, a ROM, a compact disc read-only memory (compact disc read-only memory, CD-ROM) or another optical disc memory, a magnetic disk memory or another magnetic storage device, or any other medium that is to carry or store required program code in a form of an instruction or a data structure, and may be accessed by a computer. In addition, any connection is appropriately referred to as a computer-readable medium. For example, if software is transmitted from a website, a server, or another remote source by using a coaxial cable, an optical fiber cable, a twisted pair, a digital subscriber line (Digital Subscriber Line, DSL), or wireless technologies (such as infrared, radio, and microwave), the coaxial cable, the optical fiber cable, the twisted pair, the DSL, or the wireless technologies such as infrared, radio, and microwave are included in the definition of the medium. As used herein, a magnetic disk and an optical disc include a compact disc, a laser disc, an optical disc, a digital versatile disc (Digital Versatile Disc, DVD), a floppy disk, and a Blu-ray disc, and the magnetic disk usually reproduces data magnetically, while the optical disc reproduces data optically by using a laser. A combination of the foregoing should also be included in the scope of the computer-readable medium.
An embodiment of this application provides a computer program product. The computer program product includes a computer program, and when the computer program is run, a computer is enabled to perform the foregoing method.
The embodiments of this application are described with reference to the flowcharts and/or block diagrams of the method, the device (system), and the computer program product according to the embodiments of this application. It should be understood that computer program instructions may be used to implement each procedure and/or each block in the flowcharts and/or the block diagrams and a combination of procedures and/or blocks in the flowcharts and/or the block diagrams. These computer program instructions may be provided to a general-purpose computer, a special-purpose computer, an embedded processor, or a processing unit of another programmable device to generate a machine, so that the instructions executed by the computer or the processing unit of the another programmable data processing device generate an apparatus for implementing a specific function in one or more flows in the flowcharts and/or in one or more blocks in the block diagrams.
The objectives, technical solutions, and beneficial effects of the present invention are further described in detail in the foregoing specific implementations. It should be understood that the foregoing descriptions are merely specific implementations of the present invention, but are not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, or improvement made based on the technical solutions in the present invention shall fall within the protection scope of the present invention.

Claims

A voltage control method, applied to an electronic device having a pixel circuit, wherein the pixel circuit comprises a drive module, a control end of the drive module is connected to a first node, and a source end of the drive module is connected to a second node; and the method comprises:
when driving to display a first area of a first frame of image, controlling a voltage of the first node to be a first voltage, and controlling a voltage of the second node to be a second voltage; and

when driving to display a second area of the first frame of image, controlling the voltage of the first node to be a third voltage, and controlling the voltage of the second node to be a fourth voltage, wherein

a voltage difference between the first voltage and the second voltage is greater than a voltage difference between the third voltage and the fourth voltage; and a refresh rate of the first area is a first refresh rate, a refresh rate of the second area is a second refresh rate, and the first refresh rate is less than the second refresh rate.
The method according to claim 1, wherein the first voltage is greater than the third voltage, and/or the second voltage is less than the fourth voltage.
The method according to claim 1 or 2, wherein the pixel circuit further comprises a data writing unit, the data writing unit is connected to the second node, and the data writing unit is enabled when either the first area or the second area of the first frame of image is displayed; and the method further comprises:
when driving to display the first area of a second frame of image, controlling the voltage of the first node to be the first voltage, and controlling the voltage of the second node to be the second voltage, wherein the data writing unit is disabled when the first area of the second frame of image is displayed; and

when driving to display the second area of the second frame of image, controlling the voltage of the first node to be the third voltage, and controlling the voltage of the second node to be the fourth voltage, wherein the data writing unit is enabled when the second area of the second frame of image is displayed.
The method according to claim 3, wherein the method further comprises:
when driving to display the first area of a third frame of image, controlling the voltage of the first node to be the first voltage, and controlling the voltage of the second node to be the second voltage, wherein the data writing unit is disabled when the first area of the third frame of image is displayed; and

when driving to display the second area of the third frame of image, controlling the voltage of the first node to be the third voltage, and controlling the voltage of the second node to be the fourth voltage, wherein the data writing unit is enabled when the second area of the third frame of image is displayed.
The method according to claim 4, wherein the method further comprises:
when driving to display the first area of a fourth frame of image, controlling the voltage of the first node to be the third voltage, and controlling the voltage of the second node to be the fourth voltage, wherein the data writing unit is disabled when the first area of the fourth frame of image is displayed; and

when driving to display the second area of the fourth frame of image, controlling the voltage of the first node to be the third voltage, and controlling the voltage of the second node to be the fourth voltage, wherein the data writing unit is enabled when the second area of the fourth frame of image is displayed.
The method according to claim 1 or 2, wherein the pixel circuit further comprises a data writing unit, the data writing unit is connected to the second node, and the data writing unit is enabled when either the first area or the second area of the first frame of image is displayed; and the method further comprises:
when driving to display the first area of a second frame of image, controlling the voltage of the first node to be the third voltage, and controlling the voltage of the second node to be the fourth voltage, wherein the data writing unit is disabled when the first area of the second frame of image is displayed; and

when driving to display the second area of the second frame of image, controlling the voltage of the first node to be the third voltage, and controlling the voltage of the second node to be the fourth voltage, wherein the data writing unit is enabled when the second area of the second frame of image is displayed.
The method according to any one of claims 1-6, wherein the method further comprises:
determining a start position and an end position of the first area based on an identifier of the pixel circuit corresponding to the first area; and

determining a start position and an end position of the second area based on an identifier of the pixel circuit corresponding to the second area.
The method according to any one of claims 1-7, wherein the method further comprises:
when driving to display a third area of the first frame of image, controlling the voltage of the first node to be the first voltage, and controlling the voltage of the second node to be the second voltage, wherein a refresh rate of the third area is a third refresh rate, and the third refresh rate is less than the second refresh rate.
The method according to any one of claims 1-8, wherein the drive module comprises a driving thin film transistor DTFT, a drain end of the DTFT is connected to a third node, and the DTFT is configured to output a current to the third node under control of the first node; and
the pixel circuit further comprises:
a first reset unit, connected to the first node, and configured to load a first initialized voltage to the shown first node in response to a first reset signal;

a storage capacitor, wherein one end is connected to the first node, and the other end is connected to a power supply positive electrode;

a first light-emitting control unit, connected to the power supply positive electrode and the second node, and configured to load a first power supply voltage of the power supply positive electrode to the second node in response to a light-emitting control signal;

a threshold compensation unit, connected to the first node and the third node, and configured to conduct the third node and the first node in response to a first scanning signal;

a second light-emitting control unit, connected to the third node and a fourth node, and configured to conduct the third node and the fourth node in response to a light-emitting control signal;

a light-emitting element, wherein one end is connected to the fourth node, and the other end is connected to a power supply negative electrode to load a second power supply voltage of the power supply negative electrode;

a second reset unit, connected to the fourth node, and configured to load a second initialized voltage to the fourth node in response to a second reset signal;

a data writing unit, connected to the second node, and configured to load a data voltage to the second node in response to a second scanning signal; and

a third reset unit, connected to the second node, and configured to load a third initialized voltage to the second node in response to the second reset signal.
The method according to claim 9, wherein the first reset unit comprises a first reset transistor, the first light-emitting control unit comprises a first light-emitting control transistor, the threshold compensation unit comprises a threshold compensation transistor, the second light-emitting control unit comprises a second light-emitting control transistor, the light-emitting element comprises an organic light-emitting diode OLED, the second reset unit comprises a second reset transistor, the data writing unit comprises a data writing transistor, and the third reset unit comprises a third reset transistor.
An electronic device, comprising a processor, a display driver integrated circuit DDIC, a pixel circuit, and a memory, wherein
the memory is configured to store computer-executable instructions;

the processor indicates the display driver integrated circuit to drive the pixel circuit; and

the display driver integrated circuit executes the computer-executable instructions stored in the memory, to enable the electronic device to perform the method according to any one of claims 1-10, and drive the pixel circuit.
A computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a display driver integrated circuit DDIC, the method according to any one of claims 1-10 is implemented.
A computer program product, comprising a computer program, wherein when the computer program is run, a computer is enabled to perform the method according to any one of claims 1-10.