CN111508436B - Drive circuit and display device - Google Patents
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- CN111508436B CN111508436B CN202010354093.3A CN202010354093A CN111508436B CN 111508436 B CN111508436 B CN 111508436B CN 202010354093 A CN202010354093 A CN 202010354093A CN 111508436 B CN111508436 B CN 111508436B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The application provides a driving circuit and a display device. In the application, through the voltage of the one end of dynamic change memory capacitor, make memory capacitor's electric charge amount reduce along with display device's the increase of refresh frequency, perhaps, memory capacitor's electric charge amount increases along with display device's the reduction of refresh frequency, realized data write-in process and kept pixel current ability, thereby, not only satisfy the low-power consumption demand of low refresh frequency, still satisfied the demand of the smooth picture of high refresh frequency, the circuit demand of the super wide refresh frequency has been reached, be favorable to promoting display device's picture display quality, display device's visual effect has been promoted, visual experience for the user provides the preferred, display device's competitiveness has been improved.
Description
Technical Field
The application relates to the technical field of display, in particular to a driving circuit and a display device.
Background
The screen is used as an information output port of the display device and can present various information. Currently, most display devices support a 30Hz-90Hz dynamic refresh rate. With the development of technology, the market has seen a demand for ultra-wide refresh rates of 1Hz-120 Hz. However, the conventional display device cannot satisfy the requirement of ultra-wide refresh frequency.
Disclosure of Invention
The application provides a driving circuit and a display device to solve the problem that the existing display device cannot meet the requirement of ultra-wide refresh frequency.
In a first aspect, the present application provides a driving circuit for a display device, the driving circuit comprising: a switching transistor, a driving transistor, a first storage capacitor, and a driving element; the switch transistor is electrically connected with the first end of the first storage capacitor and the driving transistor respectively, the driving transistor is electrically connected with the first end of the first storage capacitor and the driving element respectively, the second end of the first storage capacitor is electrically connected with a first voltage signal end, the amplitude of the voltage input by the first voltage signal end is reduced along with the increase of the refresh frequency of the display device, or the amplitude of the voltage input by the first voltage signal end is increased along with the reduction of the refresh frequency of the display device; the charging and discharging of the first storage capacitor are realized by controlling the on or off of the switching transistor and the driving transistor, and when the first storage capacitor is discharged, the driving element emits light according to the current provided by the driving transistor.
Optionally, the types of the driving circuit include: 2T1C, 7T1C, 6T1C or 6T 2C.
Optionally, when the driving circuit is the driving circuit of 2T1C, the switching transistor includes: a first transistor; the driving transistor includes: a second transistor; the first storage capacitor includes: a first capacitor; the drive element includes: a first light emitting diode; the first pole and the data signal end electric connection of first transistor, the grid and the scanning signal end electric connection of first transistor, the second pole of first transistor respectively with the first end of first electric capacity with the grid electricity of second transistor is connected, the first pole and the power positive voltage signal end electric connection of second transistor, the second pole of second transistor with first emitting diode's positive pole electricity is connected, first emitting transistor's negative pole and power negative voltage signal end electric connection, the second end of first electric capacity with first voltage signal end electric connection.
Alternatively, when the driving circuit is the driving circuit of 7T1C, the switching transistor and the driving transistor include: a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor; the first storage capacitor includes: a second capacitor; the drive element includes: a second light emitting diode; a gate of the third transistor is electrically connected to the first end of the second capacitor, the first pole of the fifth transistor, and the first pole of the sixth transistor, respectively, a first pole of the third transistor is electrically connected to the first pole of the fourth transistor and the first pole of the seventh transistor, respectively, and a second pole of the third transistor is electrically connected to the second pole of the fifth transistor and the first pole of the eighth transistor, respectively; the grid electrode of the fourth transistor and the grid electrode of the fifth transistor are both electrically connected with a second scanning signal end, and the second pole of the fourth transistor is electrically connected with a data signal end; a grid electrode of the sixth transistor is electrically connected with a first scanning signal end, and a second electrode of the sixth transistor and a first electrode of the ninth transistor are both electrically connected with a reference voltage signal end; the grid electrode of the seventh transistor and the grid electrode of the eighth transistor are both electrically connected with a control signal end, the second electrode of the seventh transistor is electrically connected with a power supply positive voltage signal end, the second electrode of the eighth transistor and the second electrode of the ninth transistor are both electrically connected with the anode of the second light-emitting diode, and the second end of the second light-emitting diode is electrically connected with a power supply negative voltage signal end; the grid electrode of the ninth transistor is electrically connected with a third scanning signal end, and the second end of the second capacitor is electrically connected with the first voltage signal end.
Optionally, the driving circuit further comprises: a second storage capacitor; the first end of the second storage capacitor is electrically connected with the switch transistor and the driving transistor respectively, and the second end of the second storage capacitor is electrically connected with the positive voltage signal end of the power supply.
Optionally, when the driving circuit is the driving circuit of 2T1C, the second storage capacitor includes: a third capacitor; and the first end of the third capacitor is electrically connected with the grid electrode of the second transistor, and the second end of the third capacitor is electrically connected with the positive voltage signal end of the power supply.
Optionally, when the driving circuit is the driving circuit of 7T1C, the second storage capacitor includes: a fourth capacitor; a first end of the fourth capacitor is electrically connected to the gate of the third transistor, and a second end of the fourth capacitor is electrically connected to the power supply positive voltage signal terminal.
Optionally, the frequency range of the display device is greater than or equal to 1Hz and less than or equal to 20 Hz.
Optionally, the voltage amplitude input by the first voltage signal terminal has an inverse proportional relation with the refresh frequency of the display device.
In a second aspect, the present application provides a display device comprising: m drive circuits according to the first aspect and any one of the possible designs of the first aspect, wherein M is a positive integer.
The advantages of the display device provided in the second aspect and the possible designs of the second aspect may refer to the advantages brought by the possible embodiments of the first aspect and the first aspect, and are not described herein again.
In a third aspect, the present application provides a driving circuit for a display device, the driving circuit comprising: the thin film transistor, the third storage capacitor and the liquid crystal capacitor; the grid electrode of the thin film transistor is electrically connected with a grid electrode signal end, the first electrode of the thin film transistor is electrically connected with a source electrode signal end, the second electrode of the thin film transistor is electrically connected with the first end of the third storage capacitor and the first end of the liquid crystal capacitor respectively, the second end of the third storage capacitor and the second end of the liquid crystal capacitor are both electrically connected with a second voltage signal end, the amplitude of the voltage input by the second voltage signal end is reduced along with the increase of the refresh frequency of the display device, or the amplitude of the voltage input by the second voltage signal end is increased along with the reduction of the refresh frequency of the display device.
Optionally, the driving circuit further comprises: a fourth storage capacitor; the first end of the fourth storage capacitor is electrically connected with the second electrode of the thin film transistor, and the second end of the fourth storage capacitor is electrically connected with the common voltage signal end.
Optionally, the frequency range of the display device is greater than or equal to 1Hz and less than or equal to 20 Hz.
Optionally, the voltage amplitude input by the second voltage signal terminal has an inverse proportional relation with the refresh frequency of the display device.
In a fourth aspect, the present application provides a display device comprising: n drive circuits according to any one of the possible designs of the third aspect and the fourth aspect, where N is a positive integer.
The advantageous effects of the display device provided in the fourth aspect and the possible designs of the fourth aspect may refer to the advantageous effects brought by the possible embodiments of the third aspect and the third aspect, and are not described herein again.
In a fifth aspect, the present application provides a display device comprising: m driver circuits in any one of the possible designs of the first aspect and the first aspect, and N driver circuits in any one of the possible designs of the third aspect and the third aspect, where M and N are positive integers.
The advantageous effects of the display device provided in the fifth aspect and the possible designs of the fifth aspect may refer to the advantageous effects of the possible embodiments of the first aspect and the possible embodiments of the third aspect and the third aspect, and are not described herein again.
The application provides a drive circuit and display device, through utilizing formula electric charge amount Q to become the voltage that electric capacity C voltage V comes the one end of dynamic change storage capacitor, make storage capacitor's electric charge amount reduce along with display device's the increase of refresh frequency, perhaps, storage capacitor's electric charge amount increases along with display device's the reduction of refresh frequency, data write-in process has been realized and pixel current ability has been kept, thereby, not only satisfied the low power consumption demand of low refresh frequency, the demand of the smooth picture of high refresh frequency has still been satisfied, the circuit demand of super wide refresh frequency has been reached, be favorable to promoting display device's picture display quality, display device's visual effect has been promoted, visual experience for the user provides the preferred, display device's competitiveness has been improved.
Drawings
In order to more clearly illustrate the technical solutions in the present application or the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic structural diagram of a driving circuit according to an embodiment of the present disclosure;
fig. 2 is a circuit diagram of a driving circuit according to an embodiment of the present disclosure;
fig. 3 is a circuit diagram of a driving circuit according to an embodiment of the present application;
fig. 4 is a timing diagram of a driving circuit according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a driving circuit according to an embodiment of the present application;
fig. 6 is a circuit diagram of a driving circuit according to an embodiment of the present application;
fig. 7 is a circuit diagram of a driving circuit according to an embodiment of the present application;
fig. 8 is a schematic structural diagram of a driving circuit according to an embodiment of the present application;
fig. 9 is a schematic structural diagram of a driving circuit according to an embodiment of the present application.
Description of reference numerals:
1-a drive circuit; 11-a switching transistor; 12-a drive transistor; 13 — a first storage capacitor; 14-a drive element; 15-a second storage capacitor;
t1 — first transistor; t2 — second transistor; cst1 — first capacitance; OLED1 — first light emitting diode; cst3 — third capacitance; vs1 — first voltage signal terminal; vdata — data signal terminal; Scan-Scan signal terminal; VDD-Power Positive Voltage Signal terminal; VSS — power supply negative voltage signal terminal;
t3 — third transistor; t4 — fourth transistor; t5 — fifth transistor; t6 — sixth transistor; t7 — seventh transistor; t8 — eighth transistor; t9 — ninth transistor; cst2 — second capacitance; OLED2 — second light emitting diode; cst4 — fourth capacitance; s1-first scanning signal end; s2 — second scanning signal terminal; s3 — a third scanning signal terminal; vdata — data signal terminal; vref-reference voltage signal terminal; EM-control signal terminal; VDD-Power Positive Voltage Signal terminal; VSS — power supply negative voltage signal terminal;
2-a drive circuit; 21-a thin film transistor; 22 — a third storage capacitor; 23-liquid crystal capacitance; 24-a fourth storage capacitor; Gate-Gate signal terminal; Source-Source signal terminal; vs2 — second voltage signal terminal; vcom — common voltage signal terminal.
Detailed Description
To make the purpose, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be clearly and completely described below with reference to the drawings in the present application, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone, wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a alone, b alone, or c alone, may represent: a alone, b alone, c alone, a and b in combination, a and c in combination, b and c in combination, or a, b and c in combination, wherein a, b and c may be single or multiple. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Currently, existing display devices support a 30Hz-90Hz dynamic refresh rate. The low refresh frequency is used to meet the requirement of low power consumption, and the high refresh frequency is used to meet the display requirement of high-quality pictures. Meanwhile, with the continuous progress of science and technology, the demand of ultra-wide refresh frequency of 1Hz-120Hz is already on the market. However, the existing display device cannot support the requirement of the ultra-wide refresh frequency, and the main reason is that under the condition that the refresh frequency of the display device is 1Hz, a storage capacitor in the display device needs to have an ultra-large capacitance and a thin film transistor can only support the requirement of the ultra-wide refresh frequency by only generating ultra-low leakage current; in the case where the refresh frequency of the display device is 120Hz, since the interval time period between each frame is reduced, the capacitance to be written to the storage capacitor needs to be greatly reduced. Therefore, how to arrange a reasonable storage capacitor is a problem to be solved urgently.
In order to solve the above problem, the present application provides a driving circuit and a display device, the voltage at one end of a storage capacitor is dynamically changed, based on a formula Q ═ C × V, Q is an electric charge amount, C is a capacitor, and V is a voltage, so that the electric charge amount of the storage capacitor is correspondingly changed at different refresh frequencies, thereby not only meeting the low power consumption requirement of a low refresh frequency, but also meeting the requirement of a smooth picture of a high refresh frequency, achieving the circuit requirement of an ultra-wide refresh frequency, ensuring that the display device has a high-quality display picture, and improving the competitiveness of the display device.
The voltage amplitude of one end of the storage capacitor can be set by combining with the actual circuit connection condition. For example, the application can set the inverse proportional relation between the voltage amplitude of one end of the storage capacitor and the refresh frequency of the display device, so that the voltage amplitude corresponding to the refresh frequency can be quickly and accurately determined under different refresh frequencies of the display device. The corresponding relation and the specific implementation form of the voltage amplitude are not limited, and the voltage amplitude is only required to be reduced along with the increase of the refresh frequency of the display device or increased along with the reduction of the refresh frequency of the display device.
For example, in the case of a display device with a refresh frequency of 1Hz, the voltage amplitude is a first value, such as 20V. In case the refresh frequency of the display device is 120Hz, the voltage amplitude is a second value, such as 2V, and the second value is smaller than the first value.
The display device may include, but is not limited to, any product or component having a display function, such as a display, a television, a mobile phone (mobile phone), a tablet computer (Pad), a computer, a Virtual Reality (VR) terminal, an Augmented Reality (AR) terminal, a notebook computer, a digital photo frame, and a navigator, and is not limited herein. And the present application does not limit the specific range of the refresh frequency of the display device. Optionally, the refresh frequency range of the display device is 1Hz or more and 20Hz or less.
The specific implementation manner of the driving circuit is not limited in the present application. For convenience of description, a specific implementation of the driving circuit of the present application is described in detail below with reference to the first and second scenarios. In a first scenario, the display device employs an Organic Light Emitting Diode (OLED) as a driving element, and correspondingly, the driving circuit is used for driving the OLED to emit light. In the second scenario, the display device uses a Liquid Crystal Display (LCD) to realize image display, and correspondingly, the driving circuit is used for driving the liquid crystal to enable the LCD to display under the action of the backlight source.
Scene one
Fig. 1 is a schematic structural diagram of a driving circuit according to an embodiment of the present disclosure. As shown in fig. 1, the drive circuit 1 of the present application may include: a switching transistor 11, a driving transistor 12, a first storage capacitor 13, and a driving element 14. The switching transistor 11 is electrically connected to the first terminal of the first storage capacitor 13 and the driving transistor 12, respectively, the driving transistor 12 is electrically connected to the first terminal of the first storage capacitor 13 and the driving element 14, respectively, the second terminal of the first storage capacitor 13 is electrically connected to the first voltage signal terminal Vs1, the amplitude of the voltage inputted from the first voltage signal terminal Vs1 decreases as the refresh frequency of the display device increases, or the amplitude of the voltage inputted from the first voltage signal terminal Vs1 increases as the refresh frequency of the display device decreases.
The number and types of the switching transistors 11 and the driving transistors 12 are not limited in the present application. For example, the above-mentioned Transistor may be a Thin Film Transistor (TFT), such as a P-type TFT and an N-type TFT, or a Metal Oxide semiconductor field effect Transistor (MOS) Transistor, such as a PMOS Transistor and an NMOS Transistor.
The driving element 14 may be an active-matrix organic light-emitting diode (AMOLED) panel such as an OLED. And the number and type of the first storage capacitors 13 are not limited in this application.
In the present application, the corresponding relationship between the voltage amplitude inputted from the first voltage signal terminal Vs1 and the refresh frequency of the display device is usually set in combination with the actual circuit condition, so that the voltage amplitude corresponding to the refresh frequency can be determined quickly and accurately at different refresh frequencies of the display device. The specific implementation form of the corresponding relation is not limited, and the voltage amplitude is only required to be reduced along with the increase of the refresh frequency of the display device or the voltage amplitude is increased along with the reduction of the refresh frequency of the display device.
In the present application, the switching transistor 11 is controlled to be turned on or off by inputting a signal to the switching transistor 11, and the driving transistor 12 is controlled to be turned on or off by inputting a signal to the sum driving transistor 12. Thereby, based on the mutual cooperation of the switching transistor 11 and the driving transistor 12, the charging and discharging of the first terminal of the first storage capacitor 13 can be achieved.
Further, since the charging voltage at the first terminal of the first storage capacitor 13 is kept constant, the voltage at the second terminal of the first storage capacitor 13 input by the first voltage signal terminal Vs1 decreases as the refresh frequency of the display device increases, or the voltage at the second terminal of the first storage capacitor 13 input by the first voltage signal terminal Vs1 increases as the refresh frequency of the display device decreases. The display device is provided with a plurality of pixels which are arranged in an array mode, each pixel is driven by one driving circuit 1, the OLED is a current driving device, when current flows through the OLED, the OLED emits light, and the light emitting brightness is determined by the current flowing through the OLED. Therefore, when the first storage capacitor 13 is discharged, the driving transistor 12 can supply different currents to the driving element 14 at different refresh frequencies based on the difference between the charged voltage at the first terminal of the first storage capacitor 13 and the voltage input by the first voltage signal terminal Vs1 at the second terminal of the first storage capacitor 13, so that the driving element 14 can emit light according to the current supplied by the driving transistor 12, and the light emitting condition of the driving element 14 can meet not only the low power consumption requirement of low refresh frequency, but also the requirement of smooth picture of high refresh frequency.
The application provides a drive circuit, through the switch transistor respectively with the first end of first storage capacitor and drive transistor electricity be connected, drive transistor respectively with the first end of first storage capacitor and drive element electricity be connected, the second end of first storage capacitor is connected with first voltage signal end electricity, the voltage amplitude of first voltage signal end input reduces along with the increase of display device's refresh frequency, perhaps, the voltage amplitude of first voltage signal end input increases along with the increase of display device's refresh frequency reduction. Based on the connection relation and the formula Q ═ C × V, the voltage at one end of the first storage capacitor is changed, so that the electric charge amount of the first storage capacitor is reduced along with the increase of the refresh frequency of the display device, or the electric charge amount of the first storage capacitor is increased along with the reduction of the refresh frequency of the display device, the data writing process is realized, and the pixel current capacity is kept, thereby not only meeting the low power consumption requirement of low refresh frequency, but also meeting the requirement of smooth pictures of high refresh frequency, achieving the ultra-wide circuit requirement of refresh frequency, being beneficial to improving the picture display quality of the display device, improving the visual effect of the display device, providing better visual experience for users, and improving the competitiveness of the display device.
In the present application, the type of the driving circuit 1 may include a plurality of types. Alternatively, the types of the driving circuit 1 may include: any one of 2T1C, 7T1C, 6T1C, or 6T2C drives the circuit 1. Next, a specific structure of the driving circuit 1 in the first scenario will be described by way of example in the first and second embodiments.
Example one
In the first embodiment, as shown in fig. 2, when the driving circuit 1 is the driving circuit 1 of 2T1C, the switching transistor 11 includes: the first transistor T1. The drive transistor 12 includes: and a second transistor T2. The first storage capacitor 13 includes: the first capacitor Cst 1. The drive element 14 includes: the first light emitting diode OLED 1.
A first electrode of the first transistor T1 is electrically connected to a Source signal terminal Source, a Gate electrode of the first transistor T1 is electrically connected to a Gate signal terminal Gate, a second electrode of the first transistor T1 is electrically connected to a first terminal of the first capacitor Cst1 and a Gate electrode of the second transistor T2, respectively, a first electrode of the second transistor T2 is electrically connected to a positive power supply voltage signal terminal VDD, a second electrode of the second transistor T2 is electrically connected to an anode of the first light emitting diode OLED1, a cathode of the first light emitting transistor is electrically connected to a negative power supply voltage signal terminal VSS, and a second terminal of the first capacitor Cst1 is electrically connected to a first voltage signal terminal Vs 1.
Based on the above connection relationship, the Gate of the first transistor T1 is connected to the signal input from the Gate signal terminal Gate, so that the first transistor T1 is turned on, the signal input from the Source signal terminal Source enters the first terminal of the first capacitor Cst1 and the Gate of the second transistor T2 through the first transistor T1, and the second terminal of the first capacitor Cst1 is connected to the first voltage signal terminal Vs1 for inputting different voltages at different refresh frequencies of the display device, so as to realize the charging process of the first capacitor Cst1 with different charge amounts.
Further, the Gate of the first transistor T1 is turned on by the signal inputted from the Gate signal terminal Gate, so that the first transistor T1 is turned off. Due to the storage effect of the first capacitor Cst1, the voltage at the gate of the second transistor T2 can still keep the voltage amplitude corresponding to the signal inputted from the Source terminal Source. And the first pole of the second transistor T2 is connected to the signal input from the positive voltage signal terminal VDD of the power supply, so that the second transistor T2 is turned on, the current generated by the second transistor T2 enters the first light emitting diode OLED1 through the second transistor T2, the first light emitting diode OLED1 is driven to emit light, and the light emitting condition of the first light emitting diode OLED1 can meet the requirement of the ultra-wide refresh frequency of the display device.
For example, it is assumed that the gate of the first transistor T1 can be charged to 1V. When the refresh frequency of the display device is 1Hz, the voltage inputted from the first voltage signal terminal Vs1 is 20V, and the charge amount Q of the first capacitor Cst1 is calculated as Cst (20-1) 19Cst according to the formula charge amount Q being the voltage of the capacitor C. When the refresh frequency of the display device is 120Hz, the voltage input from the first voltage signal terminal Vs1 is 2V, and the charge amount Q of the first capacitor Cst1 is calculated as Cst (2-1) Cst according to the formula charge amount Q — capacitor C voltage. Accordingly, when the refresh frequency of the display device is 1Hz, the potential holding capability of the drive circuit is preferable. When the refresh frequency of the display device is 120Hz, the potential holding capability of the drive circuit also has a certain capability. Therefore, the driving circuit 1 can satisfy the requirement of the display device for an ultra-wide refresh frequency.
Example two
In the second embodiment, as shown in fig. 3, when the driving circuit 1 is the driving circuit 1 of 7T1C, the switching transistor 11 and the driving transistor 12 include: a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9. The first storage capacitor 13 includes: and a second capacitor Cst 2. The drive element 14 includes: the second light emitting diode OLED 2.
A gate of the third transistor T3 is electrically connected to the first end of the second capacitor Cst2, the first pole of the fifth transistor T5, and the first pole of the sixth transistor T6, respectively, a first pole of the third transistor T3 is electrically connected to the first pole of the fourth transistor T4 and the first pole of the seventh transistor T7, respectively, and a second pole of the third transistor T3 is electrically connected to the second pole of the fifth transistor T5 and the first pole of the eighth transistor T8, respectively; the gate of the fourth transistor T4 and the gate of the fifth transistor T5 are both electrically connected to the second scan signal terminal S2, and the second pole of the fourth transistor T4 is electrically connected to the Source signal terminal Source; a gate of the sixth transistor T6 is electrically connected to the first scan signal terminal S1, and a second pole of the sixth transistor T6 and a first pole of the ninth transistor T9 are both electrically connected to the reference voltage signal terminal Vref; a gate of the seventh transistor T7 and a gate of the eighth transistor T8 are electrically connected to the control signal terminal EM, a second pole of the seventh transistor T7 is electrically connected to the power supply positive voltage signal terminal VDD, a second pole of the eighth transistor T8 and a second pole of the ninth transistor T9 are electrically connected to an anode of the second light emitting diode OLED2, and a second terminal of the second light emitting diode OLED2 is electrically connected to the power supply negative voltage signal terminal VSS; the gate of the ninth transistor T9 is electrically connected to the third scan signal terminal S3, and the second terminal of the second capacitor Cst2 is electrically connected to the first voltage signal terminal Vs 1.
Based on the above connection relationship, the operation principle of the drive circuit 1 of 7T1C will be described with reference to fig. 4. As shown in fig. 4, the driving circuit 1 of 7T1C is in the initialization stage when a low level signal is input from the first scan signal terminal S1, a high level signal is input from the second scan signal terminal S2, a low level signal is input from the third scan signal terminal S3, and a high level signal is input from the control signal terminal EM during a period of T1. When the driving circuit 1 of 7T1C is in the initialization stage, the ninth transistor T9 and the sixth transistor T6 are in the on state, the remaining transistors are in the off state, and the voltage of the first terminal of the second capacitor Cst2 is pulled to the voltage input from the reference voltage signal terminal, so that the second capacitor Cst2 is initialized or reset.
In the time period of T2, when a high level signal is input from the first scan signal terminal S1, a low level signal is input from the second scan signal terminal S2, a high level signal is input from the third scan signal terminal S3, and a high level signal is input from the control signal terminal EM, the drive circuit 1 of 7T1C is in the data write phase. When the driving circuit 1 of 7T1C is in the data writing phase, the fourth transistor T4 and the fifth transistor T5 are in the on state, the remaining transistors are in the off state, the voltage input from the Source signal terminal Source is written into the first terminal of the second capacitor Cst2, at this time, the voltage input from the Source signal terminal Source is the sum of the voltage input from the Source signal terminal Source and the threshold voltage of the third transistor T3 at the first terminal of the second capacitor Cst2, and at different refresh frequencies of the display device, the second terminal of the second capacitor Cst2 is connected to the first voltage signal terminal Vs1 to input different voltages, so as to realize the charging process of the second capacitor Cst2 with different charges.
In the time period of T3, when a high level signal is input from the first scan signal terminal S1, a high level signal is input from the second scan signal terminal S2, a high level signal is input from the third scan signal terminal S3, and a low level signal is input from the control signal terminal EM, the drive circuit 1 of 7T1C is in a light emitting phase. When the pixel compensation circuit is in the light emitting stage, the third transistor T3, the seventh transistor T7, and the eighth transistor T8 are in the on state, the remaining transistors are in the off state, the second capacitor Cst2 is in the discharging state, the second light emitting diode OLED2 emits light according to the flowing current, and the light emitting condition of the second light emitting diode OLED2 can meet the circuit requirement of the ultra-wide refresh frequency of the display device.
For example, it is assumed that the gate of the third transistor T3 can be charged to 1V. When the refresh frequency of the display device is 1Hz, the voltage inputted from the first voltage signal terminal Vs1 is 20V, and the charge amount Q of the second capacitor Cst2 is calculated as Cst (20-1) 19Cst according to the formula charge amount Q being the voltage of the capacitor C. When the refresh frequency of the display device is 120Hz, the voltage input from the first voltage signal terminal Vs1 is 2V, and the charge amount Q of the second capacitor Cst2 is calculated as Cst (2-1) Cst according to the formula charge amount Q being the voltage of the capacitor C. Accordingly, when the refresh frequency of the display device is 1Hz, the potential holding capability of the drive circuit is preferable. When the refresh frequency of the display device is 120Hz, the potential holding capability of the drive circuit also has a certain capability. Therefore, the driving circuit 1 can satisfy the requirement of the display device for an ultra-wide refresh frequency.
Based on the foregoing description, on the basis of the embodiment shown in fig. 1, as shown in fig. 5, the driving circuit 1 of the present application may further include: a second storage capacitor 15. A first terminal of the second storage capacitor 15 is electrically connected to the switching transistor 11 and the driving transistor 12, respectively, and a second terminal of the second storage capacitor 15 is electrically connected to the power supply positive voltage signal terminal VDD.
In the present application, the first terminal of the second storage capacitor 15 is connected to the first terminal of the first storage capacitor 13 in the same manner, so that the first terminal of the first storage capacitor 13 and the first terminal of the second storage capacitor 15 are charged and discharged in the same operation principle. The second end of the second storage capacitor 15 is connected to the voltage input by the positive voltage signal end VDD of the power supply, and the amplitude of the voltage is constant. Therefore, the charge amount of the second storage capacitor 15 after the completion of charging is constant.
Further, when the first storage capacitor 13 and the second storage capacitor 15 are discharged, since the total value of the charge amount is equal to the sum of the charge amount of the first storage capacitor 13 and the charge amount of the second storage capacitor 15, the charge amount of the first storage capacitor 13 decreases as the refresh frequency of the display device increases, and the charge amount of the second storage capacitor 15 is constant, the total value of the charge amount also decreases as the refresh frequency of the display device increases, so that the light-emitting condition of the driving element 14 can also meet the circuit requirement of the ultra-wide refresh frequency of the display device.
Or, when the first storage capacitor 13 and the second storage capacitor 15 are discharged, since the total value of the charge amount is equal to the sum of the charge amount of the first storage capacitor 13 and the charge amount of the second storage capacitor 15, the charge amount of the first storage capacitor 13 increases as the refresh frequency of the display device decreases, and the charge amount of the second storage capacitor 15 is constant, the total value of the charge amount also increases as the refresh frequency of the display device decreases, so that the light-emitting condition of the driving element 14 can also meet the circuit requirement of the ultra-wide refresh frequency of the display device.
In this application, in addition to changing the voltage of one end of the first storage capacitor 13, so that the charge amount of the first storage capacitor 13 decreases with the increase of the refresh frequency of the display device, or, so that the charge amount of the first storage capacitor 13 increases with the decrease of the refresh frequency of the display device, the driving circuit 1 may also utilize the existing structure, set the first end of the second storage capacitor 15 and the first end of the first storage capacitor 13 to be in the same connection mode, so that the working principle of charging and discharging the first end of the first storage capacitor 13 and the first end of the second storage capacitor 15 is the same, and electrically connect the second end of the second storage capacitor 15 with the positive voltage signal terminal VDD of the power supply. Accordingly, the charge amount of the second storage capacitor 15 is kept constant with the voltage input from the power supply positive voltage signal terminal VDD, the charge amount of the first storage capacitor 13 is decreased with an increase in the refresh frequency of the display device, or the charge amount of the first storage capacitor 13 is increased with a decrease in the refresh frequency of the display device. Therefore, the data writing process is realized, the pixel current capacity is kept, the low power consumption requirement of low refreshing frequency is met, the requirement of smooth pictures of high refreshing frequency is met, the ultra-wide circuit requirement of refreshing frequency is met, and meanwhile, the storage capacitor is convenient to debug subsequently.
For convenience of description, a specific structure of the driving circuit 1 including the second storage capacitor 15 in the first scenario is illustrated by the third embodiment and the fourth embodiment.
EXAMPLE III
In the third embodiment, on the basis of the embodiment shown in fig. 2, as shown in fig. 6, the second storage capacitor 15 includes: and a third capacitor Cst 3. A first terminal of the third capacitor Cst3 is electrically connected to the gate of the second transistor T2, and a second terminal of the third capacitor Cst3 is electrically connected to the power supply positive voltage signal terminal VDD.
Based on the above connection relationship, the Gate of the first transistor T1 is connected to the signal input from the Gate signal terminal Gate, so that the first transistor T1 is turned on, the signal input from the Source signal terminal Source enters the first terminal of the first capacitor Cst1, the first terminal of the third capacitor Cst3 and the Gate of the second transistor T2 through the first transistor T1, and under different refresh frequencies of the display device, the second terminal of the first capacitor Cst1 is connected to the first voltage signal terminal Vs1 to input different voltages, so as to realize the charging process of the first capacitor Cst1 with different charge amounts, and the second terminal of the third capacitor Cst3 is connected to the positive voltage signal terminal VDD to input a constant voltage, so as to complete the charging of the third capacitor Cst3 with the same charge amount.
Further, the Gate of the first transistor T1 is turned on by the signal inputted from the Gate signal terminal Gate, so that the first transistor T1 is turned off. Due to the storage effect of the first capacitor Cst1 and the third capacitor Cst3, the voltage at the gate of the second transistor T2 can still keep the voltage amplitude corresponding to the signal input from the Source terminal Source. And the first pole of the second transistor T2 is connected to the voltage input by the positive voltage signal terminal VDD of the power supply, so that the second transistor T2 is turned on, the current generated by the second transistor T2 enters the first light emitting diode OLED1 through the second transistor T2 to drive the first light emitting diode OLED1 to emit light, and the light emitting condition of the first light emitting diode OLED1 can meet the circuit requirement of the ultra-wide refresh frequency of the display device.
Example four
In the fourth embodiment, on the basis of the embodiment shown in fig. 3, as shown in fig. 7, the second storage capacitor 15 includes: and a fourth capacitor Cst 4. A first terminal of the fourth capacitor Cst4 is electrically connected to the gate of the third transistor T3, and a second terminal of the fourth capacitor Cst4 is electrically connected to the positive power supply voltage signal terminal VDD.
Based on the above connection relationship, the operation principle of the drive circuit 1 of 7T1C will be described with reference to fig. 4. As shown in fig. 4, the driving circuit 1 of 7T1C is in the initialization stage when a low level is inputted from the first scan signal terminal S1, a high level is inputted from the second scan signal terminal S2, a low level is inputted from the third scan signal terminal S3, and a high level is inputted from the control signal terminal EM at a time period T1. When the driving circuit 1 of 7T1C is in the initialization stage, the ninth transistor T9 and the sixth transistor T6 are in the on state, the remaining transistors are in the off state, and the voltage of the first terminal of the second capacitor Cst2 and the voltage of the first terminal of the fourth capacitor Cst4 are both pulled to the voltage input by the reference voltage signal terminal, so that the second capacitor Cst2 is initialized or reset.
In the time period of T2, when the high level is input from the first scan signal terminal S1, the low level is input from the second scan signal terminal S2, the high level is input from the third scan signal terminal S3, and the high level is input from the control signal terminal EM, the drive circuit 1 of 7T1C is in the data write phase. When the driving circuit 1 of 7T1C is in the data writing phase, the fourth transistor T4 and the fifth transistor T5 are in the on state, the remaining transistors are in the off state, the first terminal of the second capacitor Cst2 and the first terminal of the fourth capacitor Cst4 write the voltage input by the Source signal terminal Source, at this time, the voltage of the first terminal of the second capacitor Cst2 and the voltage of the first terminal of the fourth capacitor Cst4 are both the sum of the voltage input by the Source signal terminal Source and the threshold voltage of the third transistor T3, and at different refresh frequencies of the display device, the second terminal of the second capacitor Cst2 is connected to the first voltage terminal Vs1 to input different voltages, so as to realize the charging process of the first capacitor Cst1 with different charge amounts, and the second terminal of the fourth capacitor Cst4 is connected to the positive voltage terminal VDD to input a constant voltage, so as to realize the charging process of the constant charge amount of the fourth capacitor Cst 4.
In the time period of T3, when the high level is inputted from the first scan signal terminal S1, the high level is inputted from the second scan signal terminal S2, the high level is inputted from the third scan signal terminal S3, and the low level is inputted from the control signal terminal EM, the driving circuit 1 of 7T1C is in the light emitting phase. When the pixel compensation circuit is in the light emitting stage, the third transistor T3, the seventh transistor T7, and the eighth transistor T8 are in the on state, the remaining transistors are in the off state, the second capacitor Cst2 and the fourth capacitor Cst4 are in the discharging state, the second light emitting diode OLED2 emits light according to the flowing current, and the light emitting condition of the second light emitting diode OLED2 can meet the circuit requirement of the ultra-wide refresh frequency of the display device.
It should be noted that, in addition to the above embodiments, the driving circuit of the present application has a plurality of implementation manners, and specific implementation processes and types of the above embodiments are not described herein again.
Illustratively, the present application provides a display device. The display device may include: m drive circuits 1 shown in fig. 1 to 7, M being a positive integer.
The display device provided by the present application includes the driving circuit as described above, and the above embodiments can be implemented, and specific implementation principles and technical effects thereof can be referred to the above embodiments, which are not described herein again.
Scene two
Fig. 8 is a schematic structural diagram of a driving circuit according to an embodiment of the present application. As shown in fig. 8, the drive circuit 2 of the present application may include: a thin film transistor 21, a third storage capacitor 22, and a liquid crystal capacitor 23. The Gate of the thin film transistor 21 is electrically connected to the Gate signal terminal Gate, the first pole of the thin film transistor 21 is electrically connected to the Source signal terminal Source, the second pole of the thin film transistor 21 is electrically connected to the first terminal of the third storage capacitor 22 and the first terminal of the liquid crystal capacitor 23, the second terminal of the third storage capacitor 22 and the second terminal of the liquid crystal capacitor 23 are both electrically connected to the second voltage signal terminal Vs2, the amplitude of the voltage input from the second voltage signal terminal Vs2 decreases with the increase of the refresh frequency of the display device, or the amplitude of the voltage input from the second voltage signal terminal Vs2 increases with the decrease of the refresh frequency of the display device.
The number and type of the thin film transistors 21 are not limited in the present application. For example, the above-mentioned Transistor may be a Thin Film Transistor 21 (TFT), such as a P-type TFT and an N-type TFT, or a Metal Oxide Semiconductor (MOS) Transistor, such as a PMOS Transistor and an NMOS Transistor.
The number and type of the third storage capacitors 22 are not limited in this application. In addition, the present application generally combines the actual circuit situation to set the corresponding relationship between the voltage amplitude inputted from the second voltage signal terminal Vs2 and the refresh frequency of the display device, so as to quickly and accurately determine the voltage amplitude corresponding to the refresh frequency at different refresh frequencies of the display device. The specific implementation form of the corresponding relation is not limited, and the voltage amplitude is only required to be reduced along with the increase of the refresh frequency of the display device or the voltage amplitude is increased along with the reduction of the refresh frequency of the display device.
In this application, the Gate of the thin film transistor 21 is connected to a signal electrically input from the Gate signal terminal Gate, and is used for turning on or off the thin film transistor 21. When the tft 21 is in a conducting state, a signal inputted from the Source signal terminal Source obtains a voltage through the tft 21, and the voltage can be stored in the first terminal of the third storage capacitor 22 and the first terminal of the liquid crystal capacitor 23. And based on different refresh frequencies of the display device, the second terminal of the third storage capacitor 22 and the second terminal of the liquid crystal capacitor 23 are both connected to the second voltage signal terminal Vs2 for inputting different voltages. Then, the liquid crystal angle in the liquid crystal capacitor 23 is driven by the potential difference between the two ends of the liquid crystal capacitor 23, so that the light of the backlight source in the display device can pass through, and the picture display of the display device is realized. When the tft 21 is in the off state, the potential difference required for driving the liquid crystal capacitor 23 is continuously provided by the third storage capacitor 22, and the liquid crystal in the liquid crystal capacitor 23 can also be driven to make the light of the backlight source in the display device pass through, thereby realizing the image display of the display device. Therefore, the display condition of the display device can meet the requirements of low power consumption of low refresh frequency and smooth picture of high refresh frequency.
For example, assume that the second pole of the thin film transistor 21 can be charged to 1V. When the refresh frequency of the display device is 1Hz, the voltage inputted from the second voltage signal terminal Vs2 is 20V, and the charge amount Q of the third storage capacitor 22 becomes Cst (20-1) 19Cst according to the formula Q ═ C × V. When the refresh frequency of the display device is 120Hz, the voltage input from the second voltage signal terminal Vs2 is 2V, and the charge amount Q of the third storage capacitor 22 is calculated as Cst (2-1) Cst according to the formula charge amount Q being the voltage of the capacitor C. Accordingly, when the refresh frequency of the display device is 1Hz, the potential holding capability of the drive circuit is preferable. When the refresh frequency of the display device is 120Hz, the potential holding capability of the drive circuit also has a certain capability. Therefore, the driving circuit 2 can satisfy the requirement of the display device for an ultra-wide refresh frequency.
The application provides a drive circuit, gate and scanning signal end electric connection through thin-film transistor, thin-film transistor's first pole and data signal end electric connection, thin-film transistor's second pole is connected with third storage capacitor's first end and liquid crystal capacitor's first end electricity respectively, third storage capacitor's second end and liquid crystal capacitor's second end all are connected with second voltage signal end electric connection, the voltage amplitude of second voltage signal end input reduces along with the increase of display device's frequency, perhaps, the voltage amplitude of second voltage signal end input increases along with the reduction of display device's refresh frequency. Based on the above connection relationship and formula, the charge amount Q is equal to the voltage C, the voltage of one end of the third storage capacitor is changed, so that the charge amount of the third storage capacitor is reduced along with the increase of the refresh frequency of the display device, or the charge amount of the third storage capacitor is increased along with the reduction of the refresh frequency of the display device, the data writing process is realized, and the pixel current capacity is maintained, thereby not only meeting the low power consumption requirement of low refresh frequency, but also meeting the requirement of smooth pictures of high refresh frequency, achieving the circuit requirement of ultra-wide refresh frequency, being beneficial to improving the picture display quality of the display device, improving the visual effect of the display device, providing better visual experience for users, and improving the competitiveness of the display device.
Based on the foregoing description, on the basis of the embodiment shown in fig. 8, as shown in fig. 9, the driving circuit 2 of the present application may further include: a fourth storage capacitor 24. A first terminal of the fourth storage capacitor 24 is electrically connected to the second electrode of the thin film transistor 21, and a second terminal of the fourth storage capacitor 24 is electrically connected to the common voltage signal terminal Vcom.
In the present application, the first terminal of the fourth storage capacitor 24 is connected to the first terminal of the third storage capacitor 22 in the same manner, so that the first terminal of the third storage capacitor 22 and the first terminal of the fourth storage capacitor 24 are charged and discharged in the same operation principle. Since the second terminal of the fourth storage capacitor 24 is connected to the voltage input by the common voltage signal terminal Vcom, the amplitude of the voltage is constant. Therefore, the charge amount of the fourth storage capacitor 24 after the completion of charging is constant.
Further, when the third storage capacitor 22 and the fourth storage capacitor 24 are discharged, since the total value of the charge amount is equal to the sum of the charge amount of the third storage capacitor 22 and the charge amount of the fourth storage capacitor 24, the charge amount of the third storage capacitor 22 decreases as the refresh frequency of the display device increases, and the charge amount of the fourth storage capacitor 24 is constant, the total value of the charge amount also decreases as the refresh frequency of the display device increases, so that the display condition of the display device can also meet the requirement of the display device for an ultra-wide refresh frequency.
Or, when the third storage capacitor 22 and the fourth storage capacitor 24 are discharged, since the total value of the charge amount is equal to the sum of the charge amount of the third storage capacitor 22 and the charge amount of the fourth storage capacitor 24, the charge amount of the third storage capacitor 22 increases as the refresh frequency of the display device decreases, and the charge amount of the fourth storage capacitor 24 is constant, the total value of the charge amount also increases as the refresh frequency of the display device decreases, so that the display condition of the display device can also meet the requirement of the display device for an ultra-wide refresh frequency.
In the present application, in addition to changing the voltage of one end of the third storage capacitor 22, so that the charge amount of the third storage capacitor 22 decreases with the increase of the refresh frequency of the display device, or, so that the charge amount of the third storage capacitor 22 increases with the decrease of the refresh frequency of the display device, the driving circuit 1 may also utilize the existing structure to set the first end of the fourth storage capacitor 24 and the first end of the third storage capacitor 22 to the same connection mode, so that the working principle of charging and discharging the first end of the fourth storage capacitor 24 and the first end of the third storage capacitor 22 is the same, and the second end of the fourth storage capacitor 24 is electrically connected to the common voltage signal terminal Vcom. Accordingly, the charge amount of the fourth storage capacitor 24 is kept constant with the voltage input from the common voltage signal terminal Vcom, the charge amount of the third storage capacitor 22 is decreased with the increase of the refresh frequency of the display device, or the charge amount of the third storage capacitor 22 is increased with the decrease of the refresh frequency of the display device. Therefore, the data writing process is realized, the pixel current capacity is kept, the low power consumption requirement of low refreshing frequency is met, the requirement of smooth pictures of high refreshing frequency is met, the ultra-wide circuit requirement of refreshing frequency is met, and meanwhile, the storage capacitor is convenient to debug subsequently.
Illustratively, the present application provides a display device. The display device may include: n drive circuits 2 shown in fig. 8 to 9, N being a positive integer.
The display device provided by the present application includes the driving circuit as described above, and the above embodiments can be implemented, and specific implementation principles and technical effects thereof can be referred to the above embodiments, which are not described herein again.
It should be noted that, in addition to M driving circuits 1 shown in fig. 1 to 7 or N driving circuits 2 shown in fig. 8 to 9, the display device may also include M driving circuits 1 shown in fig. 1 to 7 and N driving circuits 2 shown in fig. 8 to 9.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (10)
1. A driving circuit applied to a display device, the driving circuit comprising: a switching transistor, a driving transistor, a first storage capacitor, and a driving element; the switch transistor is electrically connected with a first end of the first storage capacitor and the driving transistor respectively, a gate of the driving transistor is electrically connected with the first end of the first storage capacitor, a source or a drain of the driving transistor is electrically connected with the driving element, a second end of the first storage capacitor is electrically connected with a first voltage signal end, and the amplitude of the voltage input by the first voltage signal end is reduced along with the increase of the refresh frequency of the display device, or the amplitude of the voltage input by the first voltage signal end is increased along with the decrease of the refresh frequency of the display device;
the charging and discharging of the first storage capacitor are realized by controlling the on or off of the switching transistor and the driving transistor, and when the first storage capacitor is discharged, the driving element emits light according to the current provided by the driving transistor.
2. The driving circuit according to claim 1, wherein the type of the driving circuit comprises: 2T1C, 7T1C, 6T1C or 6T 2C.
3. The drive circuit according to claim 2,
when the driving circuit is the driving circuit of 2T1C, the switching transistor includes: a first transistor; the driving transistor includes: a second transistor; the first storage capacitor includes: a first capacitor; the drive element includes: a first light emitting diode;
the first pole and the data signal end electric connection of first transistor, the grid and the scanning signal end electric connection of first transistor, the second pole of first transistor respectively with the first end of first electric capacity with the grid electricity of second transistor is connected, the first pole and the power positive voltage signal end electric connection of second transistor, the second pole of second transistor with first emitting diode's positive pole electricity is connected, first emitting diode's negative pole and power negative voltage signal end electric connection, the second end of first electric capacity with first voltage signal end electric connection.
4. The drive circuit according to claim 2,
when the driving circuit is the driving circuit of 7T1C, the switching transistor and the driving transistor include: a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor; the first storage capacitor includes: a second capacitor; the drive element includes: a second light emitting diode;
a gate of the third transistor is electrically connected to the first end of the second capacitor, the first pole of the fifth transistor, and the first pole of the sixth transistor, respectively, a first pole of the third transistor is electrically connected to the first pole of the fourth transistor and the first pole of the seventh transistor, respectively, and a second pole of the third transistor is electrically connected to the second pole of the fifth transistor and the first pole of the eighth transistor, respectively;
the grid electrode of the fourth transistor and the grid electrode of the fifth transistor are both electrically connected with a second scanning signal end, and the second pole of the fourth transistor is electrically connected with a data signal end;
a grid electrode of the sixth transistor is electrically connected with a first scanning signal end, and a second electrode of the sixth transistor and a first electrode of the ninth transistor are both electrically connected with a reference voltage signal end;
the grid electrode of the seventh transistor and the grid electrode of the eighth transistor are both electrically connected with a control signal end, the second electrode of the seventh transistor is electrically connected with a power supply positive voltage signal end, the second electrode of the eighth transistor and the second electrode of the ninth transistor are both electrically connected with the anode of the second light-emitting diode, and the second end of the second light-emitting diode is electrically connected with a power supply negative voltage signal end;
the grid electrode of the ninth transistor is electrically connected with a third scanning signal end, and the second end of the second capacitor is electrically connected with the first voltage signal end.
5. The drive circuit according to any one of claims 1 to 4, wherein the drive circuit further comprises: a second storage capacitor; the first end of the second storage capacitor is electrically connected with the switch transistor and the driving transistor respectively, and the second end of the second storage capacitor is electrically connected with a positive voltage signal end of a power supply.
6. The drive circuit according to claim 5,
when the driving circuit is a driving circuit of 2T1C, the second storage capacitor includes: a third capacitor; and the first end of the third capacitor is electrically connected with the grid electrode of the second transistor, and the second end of the third capacitor is electrically connected with the positive voltage signal end of the power supply.
7. The drive circuit according to claim 5,
when the driving circuit is the driving circuit of 7T1C, the second storage capacitor includes: a fourth capacitor; the first end of the fourth capacitor is electrically connected with the grid electrode of the third transistor, and the second end of the fourth capacitor is electrically connected with the positive voltage signal end of the power supply.
8. The driver circuit according to any one of claims 1 to 4, wherein the frequency range of the display device is 1Hz or more and 20Hz or less.
9. The driving circuit according to any of claims 1-4, wherein the magnitude of the voltage input to the first voltage signal terminal has an inverse proportional relationship with the refresh frequency of the display device.
10. A display device, comprising: m drive circuits according to any of claims 1-9, M being a positive integer.
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| JP2002278517A (en) * | 2001-03-15 | 2002-09-27 | Hitachi Ltd | Liquid crystal display |
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| CN102967974B (en) * | 2012-11-08 | 2016-03-30 | 京东方科技集团股份有限公司 | A kind of array base palte, display device and refreshing frequency control method |
| KR102348062B1 (en) * | 2017-04-04 | 2022-01-10 | 삼성디스플레이 주식회사 | Organic light emitting display device and driving method thereof |
| CN110197644A (en) * | 2019-06-10 | 2019-09-03 | 武汉华星光电半导体显示技术有限公司 | Pixel-driving circuit |
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