EP4693269A1

EP4693269A1 - Pixel drive circuit and display panel

Info

Publication number: EP4693269A1
Application number: EP23930003.1A
Authority: EP
Inventors: Weigao CHENG
Original assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2023-03-30
Filing date: 2023-11-28
Publication date: 2026-02-11
Also published as: WO2024198436A1; CN117475918A

Abstract

The present application discloses a pixel driving circuit and a display panel. A writing frame of the pixel driving circuit includes a first reset phase and a data writing phase performed in sequence. In the first reset phase, a first light-emitting control module is configured to write a first power supply signal into a first electrode and a second electrode of a driving transistor, or a first initialization module and a second light-emitting control module are configured to write a first initialization signal into the first electrode and the second electrode of the driving transistor.

Description

TECHNICAL FIELD

The present application relates to the field of display technology, and specifically relates to a pixel driving circuit and a display panel.

BACKGROUND

With the continuous development of AMOLED (Active-Matrix Organic Light-Emitting Diode) display panels in the consumer market, consumers have increasingly high requirements for the optical performance of AMOLED display panels. As an index for evaluating the optical performance of AMOLED display panels, Flicker (image flicker) is of great significance in guiding researchers to research and develop AMOLED display panels.
Currently, AMOLED display panels have a serious problem of image flicker during low-frequency display.
The specific reason is as follows: During low-frequency display of an AMOLED display panel, a displayed frame of display image usually includes a writing frame and a holding frame. The holding frame includes at least one sub-frame. During the writing frame and the first sub-frame of the holding frame, there is a difference in the effect of resetting the characteristics of the driving transistor of the AMOLED display panel, which leads to a difference between the brightness of the AMOLED display panel in the writing frame and the brightness in the first sub-frame of the holding frame, thereby causing the problem of image flicker.

SUMMARY

The present application provides a pixel driving circuit and a display panel, aiming to solve the technical problem in the existing technology where a display panel has image flicker due to a brightness difference between a writing frame and the first sub-frame of a holding frame.
In a first aspect, the present application provides a pixel driving circuit, including:

a driving transistor;
a first light-emitting control module, where a control terminal of the first light-emitting control module is configured to access a first enable signal, an input terminal of the first light-emitting control module is configured to access a first power supply signal, and an output terminal of the first light-emitting control module is electrically connected to a first electrode of the driving transistor;
a second light-emitting control module, where a control terminal of the second light-emitting control module is configured to access a second enable signal, and an output terminal of the second light-emitting control module is electrically connected to a second electrode of the driving transistor;
a data writing module, where a first control terminal of the data writing module is configured to access a first control signal, a second control terminal of the data writing module is configured to access a second control signal, an input terminal of the data writing module is configured to access a data signal, where the data writing module is further electrically connected to a gate, the first electrode, and the second electrode of the driving transistor; and
a first initialization module, where a control terminal of the first initialization module is configured to access a third control signal, an input terminal of the first initialization module is configured to access a first initialization signal, and an output terminal of the first initialization module is electrically connected to an input terminal of the second light-emitting control module;
where a driving timing sequence of the pixel driving circuit includes a writing frame and a holding frame, and the writing frame includes a first reset phase and a data writing phase performed in sequence; where in the first reset phase, the first light-emitting control module is configured to write the first power supply signal into the first electrode and the second electrode of the driving transistor, or the first initialization module and the second light-emitting control module are configured to write the first initialization signal into the first electrode and the second electrode of the driving transistor.

Optionally, in some embodiments of the present application, the holding frame includes at least one sub-frame; and when brightness of the writing frame is less than brightness of the first sub-frame of the holding frame, the first power supply signal is written into the first electrode and the second electrode of the driving transistor in the first reset phase by the first light-emitting control module in response to the first enable signal.
Optionally, in some embodiments of the present application, the first control signal and the third control signal are the same signal.
Optionally, in some embodiments of the present application, the pixel driving circuit further includes a second initialization module, where a control terminal of the second initialization module is configured to access a fourth control signal, an input terminal of the second initialization module is configured to access a second initialization signal, and an output terminal of the second initialization module is electrically connected to the gate of the driving transistor;
where in the first reset phase, the second initialization module writes the second initialization signal into the gate of the driving transistor in response to the fourth control signal.
Optionally, in some embodiments of the present application, the second initialization module includes a fifth transistor, where a gate of the fifth transistor is configured to access the fourth control signal, one of a source and a drain of the fifth transistor is configured to access the second initialization signal, and another of the source and the drain of the fifth transistor is electrically connected to the gate of the driving transistor.
Optionally, in some embodiments of the present application, the fifth transistor is an N-type oxide transistor.
Optionally, in some embodiments of the present application, the holding frame includes at least one sub-frame; and when brightness of the writing frame is greater than brightness of a first sub-frame of the holding frame, the first initialization signal is written into the first electrode and the second electrode of the driving transistor in the first reset phase by the first initialization module in response to the third control signal and by the second light-emitting control module in response to the second enable signal.
Optionally, in some embodiments of the present application, the pixel driving circuit further includes a second initialization module, where a control terminal of the second initialization module is configured to access a fourth control signal, an input terminal of the second initialization module is configured to access a second initialization signal, and an output terminal of the second initialization module is electrically connected to the gate of the driving transistor;

where the writing frame further includes a second reset phase, and the second reset phase is presented between the first reset phase and the data writing phase;
where in the second reset phase, the second initialization module writes the second initialization signal into the gate of the driving transistor in response to the fourth control signal.

Optionally, in some embodiments of the present application, the first control signal and the third control signal are different signals.
Optionally, in some embodiments of the present application, the first light-emitting control module includes a first transistor, where a gate of the first transistor is configured to access the first enable signal, one of a source and a drain of the first transistor is configured to access the first power supply signal, and another of the source and the drain of the first transistor is electrically connected to the first electrode of the driving transistor.
Optionally, in some embodiments of the present application, the second light-emitting control module includes a second transistor, where a gate of the second transistor is configured to access the second enable signal, one of a source and a drain of the second transistor is electrically connected to the second electrode of the driving transistor, and another of the source and the drain of the second transistor is electrically connected to the first initialization module.
Optionally, in some embodiments of the present application, the data writing module includes a third transistor and a fourth transistor, where a gate of the third transistor is configured to access the first control signal, one of a source and a drain of the third transistor is configured to access the data signal, another of the source and the drain of the third transistor is electrically connected to the first electrode of the driving transistor, a gate of the fourth transistor is configured to access the second control signal, one of the source and the drain of the fourth transistor is electrically connected to the second electrode of the driving transistor, and another of the source and the drain of the fourth transistor is electrically connected to the gate of the driving transistor.
Optionally, in some embodiments of the present application, the first initialization module includes a sixth transistor, where a gate of the sixth transistor is configured to access the third control signal, one of a source and a drain of the sixth transistor is configured to access the first initialization signal, and another of the source and the drain of the sixth transistor is electrically connected to the second light-emitting control module.
Optionally, in some embodiments of the present application, the pixel driving circuit further includes a first capacitor, where one electrode plate of the first capacitor is electrically connected to the gate of the driving transistor, and another electrode plate of the first capacitor is configured to access the first power supply signal.
Optionally, in some embodiments of the present application, the pixel driving circuit further includes a second capacitor, where one electrode plate of the second capacitor is electrically connected to the gate of the driving transistor, and another electrode plate of the second capacitor is configured to access the first control signal.
Optionally, in some embodiments of the present application, the first light-emitting control module includes a first transistor, where a gate of the first transistor is configured to access the first enable signal, one of a source and a drain of the first transistor is configured to access the first power supply signal, and another of the source and the drain of the first transistor is electrically connected to the first electrode of the driving transistor;

the second light-emitting control module includes a second transistor, where a gate of the second transistor is configured to access the second enable signal, and one of a source and a drain of the second transistor is electrically connected to the second electrode of the driving transistor;
the data writing module includes a third transistor and a fourth transistor, where a gate of the third transistor is configured to access the first control signal, one of a source and a drain of the third transistor is configured to access the data signal, another of the source and the drain of the third transistor is electrically connected to the first electrode of the driving transistor, a gate of the fourth transistor is configured to access the second control signal, one of the source and the drain of the fourth transistor is electrically connected to the gate of the driving transistor, and another of the source and the drain of the fourth transistor is electrically connected to the second electrode of the driving transistor;
the first initialization module includes a sixth transistor, where a gate of the sixth transistor is configured to access the third control signal, one of a source and a drain of the sixth transistor is configured to access the first initialization signal, and another of the source and the drain of the sixth transistor is electrically connected to another of the source and the drain of the second transistor; and
the first transistor, the driving transistor, the second transistor, the third transistor, and the sixth transistor are P-type low-temperature polysilicon transistors, and the fourth transistor is an N-type oxide transistor.

Optionally, in some embodiments of the present application, the driving timing sequence of the pixel driving circuit further includes a third reset phase and a light-emitting phase after the data writing phase;

in the data writing phase, the data writing module transmits the compensated data signal to the gate of the driving transistor in response to the first control signal and the second control signal;
in the third reset phase, the first light-emitting control module writes the first power supply signal into the first electrode and the second electrode of the driving transistor in response to the first enable signal; and
in the light-emitting phase, a light-emitting device is controlled to emit light by the first light-emitting control module in response to the first enable signal and by the second light-emitting control module in response to the second enable signal.

Optionally, in some embodiments of the present application, in the holding frame, the data writing module is further configured to write the data signal into the first electrode and the second electrode of the driving transistor at least one time.
In a second aspect, the present application further provides a display panel, where the display panel includes a plurality of pixel units arranged in an array, and the pixel units include the above-mentioned pixel driving circuit.

BENEFICIAL EFFECTS

The present application provides a pixel driving circuit and a display panel. The pixel driving circuit includes a first light-emitting control module, a driving transistor, a second light-emitting control module, a data writing module, and a first initialization module. In the present application, before the data writing phase, the first power supply signal is written into the first electrode and the second electrode of the driving transistor through the first light-emitting control module, or the first initialization signal is written into the first electrode and the second electrode of the driving transistor through the first initialization module and the second light-emitting control module, so as to reset the potentials of the first electrode and the second electrode of the driving transistor. Thereby, the gate-source voltage of the driving transistor is changed, and the reset effect of the driving transistor in the writing frame is adjusted, which can reduce the difference in the characteristic reset effect of the driving transistor between the writing frame and the holding frame, further reduce the brightness difference between the writing frame and the holding frame, and improve image flicker.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a first circuit structure of the pixel driving circuit provided by an embodiment of the present application;
FIG. 2 is a schematic diagram of a signal timing sequence of a writing frame of the pixel driving circuit shown in FIG. 1;
FIG. 3 is a schematic diagram of a second circuit structure of the pixel driving circuit provided by an embodiment of the present application;
FIG. 4 is a schematic diagram of a signal timing sequence of a writing frame of the pixel driving circuit shown in FIG. 3;
FIG. 5 is a schematic diagram of signal timing sequences of a writing frame and a holding frame of the pixel driving circuit shown in FIG. 1;
FIG. 6 is a schematic diagram of a structure of the display panel provided by an embodiment of the present application.

DETAILED DESCRIPTION

The following will describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. The described embodiments are only used to explain the ideas of the invention and should not be regarded as limiting the protection scope of the present application.
In the description of the present application, it should be understood that the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, features defined with "first", "second", etc. may explicitly or implicitly include one or more of the features, and thus cannot be understood as limiting the present application. In addition, it should be noted that unless otherwise clearly specified and limited, the terms "connected" and "connection" should be understood in a broad sense. For example, they may be mechanical connections or electrical connections; they may be direct connections or indirect connections through an intermediate medium, or they may be internal communication between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.
The present application provides a pixel driving circuit and a display panel, which will be described in detail below. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments of the present application.
Please refer to FIG. 1 to FIG. 3. FIG. 1 is a schematic diagram of a first circuit structure of the pixel driving circuit provided by an embodiment of the present application, FIG. 2 is a schematic diagram of a signal timing sequence of a writing frame of the pixel driving circuit shown in FIG. 1, and FIG. 3 is a schematic diagram of a second circuit structure of the pixel driving circuit provided by an embodiment of the present application. In embodiments of the present application, the pixel driving circuit 100 includes a first light-emitting control module 101, a driving transistor TD, a second light-emitting control module 102, a data writing module 103, and a first initialization module 105.
A control terminal of the first light-emitting control module 101 is configured to access a first enable signal EM_L. An input terminal of the first light-emitting control module 101 is configured to access a first power supply signal ELVDD. An output terminal of the first light-emitting control module 101 is electrically connected to a first node A.
The first light-emitting control module 101 includes but is not limited to a first transistor T1. A gate of the first transistor T1 is configured to access the first enable signal EM_L. One of a source and a drain of the first transistor T1 is configured to access the first power supply signal ELVDD. Another of the source and the drain of the first transistor T1 is electrically connected to the first node A.
A first electrode of the driving transistor TD is electrically connected to the first node A. A second electrode of the driving transistor TD is electrically connected to a second node B. A gate of the driving transistor TD is electrically connected to a third node Q.
The first electrode is one of a source and a drain of the driving transistor TD, and the second electrode is another of the source and the drain of the driving transistor TD.
A control terminal of the second light-emitting control module 102 is configured to access a second enable signal EM_R. An input terminal of the second light-emitting control module 102 is electrically connected to the second node B. An output terminal of the second light-emitting control module 102 is electrically connected to a fourth node C, that is, electrically connected to an output terminal of the first initialization module 105.
The second light-emitting control module 102 includes but is not limited to a second transistor T2. A gate of the second transistor T2 is configured to access the second enable signal EM_R. One of a source and a drain of the second transistor T2 is electrically connected to the second node B. Another of the source and the drain of the second transistor T2 is electrically connected to the fourth node C.
A first control terminal of the data writing module 103 is configured to access a first control signal PScan(n). A second control terminal of the data writing module 103 is configured to access a second control signal NScan(n+10). An input terminal of the data writing module 103 is configured to access a data signal Data. The data writing module 103 is further electrically connected to the first node A, the second node B, and the third node Q.
The data writing module 103 includes but is not limited to a third transistor T3 and a fourth transistor T4. A gate of the third transistor T3 is configured to access the first control signal PScan(n). One of a source and a drain of the third transistor T3 is configured to access the data signal Data. Another of the source and the drain of the third transistor T3 is electrically connected to the first node A. A gate of the fourth transistor T4 is configured to access the second control signal NScan(n+10). One of a source and a drain of the fourth transistor T4 is electrically connected to the second node B. Another of the source and the drain of the fourth transistor T4 is electrically connected to the third node Q.
A control terminal of the first initialization module 105 is configured to access a third control signal PScan(n)/PScan(n-1). An input terminal of the first initialization module 105 is configured to access a first initialization signal Vi1.
The first initialization module 105 includes but is not limited to a sixth transistor T6. A gate of the sixth transistor T6 is configured to access the third control signal PScan(n)/PScan(n-1). One of a source and a drain of the sixth transistor T6 is configured to access the first initialization signal Vi1. Another of the source and the drain of the sixth transistor T6 is electrically connected to the fourth node C.
In embodiments of the present application, the driving timing sequence of the pixel driving circuit 100 includes a writing frame and a holding frame. The writing frame includes a first reset phase M1 and a data writing phase M2 performed in sequence. In the first reset phase M1, the first electrode and the second electrode of the driving transistor TD are written with the first power supply signal ELVDD or the first initialization signal Vi1.
The writing frame includes one sub-frame, and the holding frame includes at least one sub-frame. It can be understood that the display panel may include multiple display frequencies, such as 30Hz, 60Hz, 120Hz, etc. For example, taking 120Hz as a reference, when the display panel displays at 120Hz, the driving timing sequence of the pixel driving circuit 100 only includes a writing frame, and the writing frame includes one sub-frame. When the display panel displays at 30Hz, the driving timing sequence of the pixel driving circuit 100 includes a writing frame and a holding frame. The writing frame includes one sub-frame, and the holding frame includes three sub-frames. That is, when the display panel displays at 120Hz, one frame of display image includes one sub-frame. When the display panel displays at 30Hz, which is low-frequency display, one frame of display image includes three sub-frames. The pixel driving circuit 100 writes the compensated data signal Data into the gate of the driving transistor TD only in the writing frame.
In the pixel driving circuit 100 provided by embodiments of the present application, before the data writing phase M2, the first power supply signal ELVDD is written into the first electrode and the second electrode of the driving transistor DT through the first light-emitting control module 101, or the first initialization signal Vi1 is written into the first electrode and the second electrode of the driving transistor TD through the first initialization module 105 and the second light-emitting control module 102, so as to reset the potentials of the first electrode and the second electrode of the driving transistor TD. Thus, by changing the gate-source voltage Vgs of the driving transistor TD, the reset effect of the driving transistor TD in the writing frame is adjusted, the difference in the characteristic reset effect of the driving transistor TD between the writing frame and the first sub-frame of the holding frame is reduced, further reducing the brightness difference between the writing frame and the first sub-frame of the holding frame, and improving image flicker.
In some embodiments of the present application, the pixel driving circuit 100 further includes a second initialization module 104, a first capacitor Cst, and a light-emitting device D.
A control terminal of the second initialization module 104 is configured to access a fourth control signal NScan(n). An input terminal of the second initialization module 104 is configured to access a second initialization signal Vi2. An output terminal of the second initialization module 104 is connected to the third node Q.
The second initialization module 104 includes but is not limited to a fifth transistor T5. A gate of the fifth transistor T5 is configured to access the fourth control signal NScan(n). One of a source and a drain of the fifth transistor T5 is configured to access the second initialization signal Vi2. Another of the source and the drain of the fifth transistor T5 is connected to the third node Q.
One electrode plate of the first capacitor Cst is connected to the third node Q. Another electrode plate of the first capacitor Cst is configured to access the first power supply signal ELVDD.
One end of the light-emitting device D is connected to the fourth node C. Another end of the light-emitting device D is configured to access a second power supply signal VSS.
The voltage of the first power supply signal ELVDD is greater than the voltage of the second power supply signal VSS. The light-emitting device D may be a mini light-emitting diode, a micro light-emitting diode, or an organic light-emitting diode, which is not specifically limited in embodiments of the present application.
It should be noted that the transistors adopted in all embodiments of the present application may be thin-film transistors, field-effect transistors, or other devices with the same characteristics, and the source and drain of the transistor are interchangeable. In embodiments of the present application, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the source, and another electrode is referred to as the drain. According to the form in the drawings, the middle terminal of the transistor is the gate, the signal input terminal is the drain, and the output terminal is the source. In addition, the transistors adopted in the embodiments of the present application may include P-type transistors and/or N-type transistors. Among them, the P-type transistor is turned on when the gate is at a low level and is turned off when the gate is at a high level; the N-type transistor is turned on when the gate is at a high level and is turned off when the gate is at a low level.
In addition, to improve the performance of the pixel driving circuit 100, the transistors provided in the embodiments of the present application are low-temperature polysilicon thin-film transistors and oxide semiconductor thin-film transistors. The oxide semiconductor thin-film transistors may be oxide thin-film transistors, such as indium gallium zinc oxide thin-film transistors. In embodiments of the present application, the above two types of thin-film transistors are applied in the same pixel driving circuit 100, and the oxide thin-film transistor is used as a device at a position with large leakage current in the pixel driving circuit 100, so as to effectively prevent the charge at the gate of the corresponding driving transistor TD from leaking during low-frequency driving and further prevent the problem of image flicker in the display image.
Specifically, the following embodiments of the present application are described by taking that the first transistor T1, the driving transistor TD, the second transistor T2, the third transistor T3, and the sixth transistor T6 in the pixel driving circuit 100 are P-type low-temperature polysilicon transistors, and the fourth transistor T4 and the fifth transistor T5 are N-type oxide transistors as examples, but this cannot be understood as a limitation to the present application.
Please continue to refer to FIG. 1 and FIG. 2. In some embodiments of the present application, the holding frame includes at least one sub-frame. When the brightness of the writing frame is less than the brightness of the first sub-frame of the holding frame, the first power supply signal ELVDD is written into the first electrode and the second electrode of the driving transistor TD in the first reset phase M1 by the first light-emitting control module 101 in response to the first enable signal EM_L.
Specifically, in the first reset phase M1, the first enable signal EM_L is at a low level, and the first transistor T1 is turned on. The first power supply signal ELVDD is written into the first electrode and the second electrode of the driving transistor TD through the first transistor T1 and the driving transistor TD.
Further, in the first reset phase M1, the second initialization module 104 writes the second initialization signal Vi2 into the gate of the driving transistor TD in response to the fourth control signal NScan(n).
Specifically, in the first reset phase M1, the fourth control signal NScan(n) is at a high level, and the fifth transistor T5 is turned on. The second initialization signal Vi2 is written into the gate of the driving transistor TD through the fifth transistor T5.
That is, in embodiments of the present application, both the first light-emitting control module 101 and the second initialization module 104 operate in the first reset phase M1. Of course, by controlling the timing sequences of the fourth control signal NScan(n) and the first enable signal EM_L, the first light-emitting control module 101 and the second initialization module 104 can also be controlled to operate in phases, which is not specifically limited in the present application.
It can be understood that writing the first power supply signal ELVDD into the first electrode and the second electrode of the driving transistor TD can make the gate-source voltage Vgs of the driving transistor TD be at a fixed value, that is, Vgs=Vgd=Vi2-ELVDD. Since the voltage value of the first power supply signal ELVDD is relatively large, the voltage difference of Vgs/Vgd is increased, that is, the characteristic reset effect of the driving transistor TD is enhanced, which can effectively improve the brightness of the display panel in the writing frame and improve the flicker caused by the low brightness of the writing frame.
In embodiments of the present application, in the data writing phase M2, the data writing module 103 transmits the compensated data signal Data to the third node Q in response to the first control signal PScan(n) and the second control signal NScan(n+10), that is, writes the compensated data signal into the gate of the driving transistor TD.
Specifically, in the data writing phase M2, the first control signal PScan(n) is at a low level, the second control signal NScan(n+10) is at a high level, and both the third transistor T3 and the fourth transistor T4 are turned on. The data writing phase M2 includes compensation for the threshold voltage of the driving transistor TD. Therefore, the compensated data signal, specifically Vdata+Vth, is written into the third node Q, where Vth is the threshold voltage of the driving transistor.
In embodiments of the present application, the first control signal PScan(n) and the third control signal PScan(n) are the same signal. Thus, in the data writing phase M2, the first initialization module 105 and the data writing module 103 operate simultaneously. The first initialization module 105 writes the first initialization signal Vi1 into the fourth node C in response to the third control signal PScan(n), thereby resetting the anode of the light-emitting device D and improving display uniformity.
Specifically, in the data writing phase M2, the third control signal PScan(n) is at a low level, and the sixth transistor T6 is turned on. The first initialization signal Vi1 is written into the fourth node C through the sixth transistor T6.
In embodiments of the present application, the driving timing sequence of the pixel driving circuit 100 further includes a third reset phase M3 and a light-emitting phase M4 after the data writing phase M2.
In the third reset phase M3, the first light-emitting control module 101 writes the first power supply signal ELVDD into the first electrode and the second electrode of the driving transistor TD in response to the first enable signal EM_L.
Specifically, in the third reset phase M3, the first enable signal EM_L is at a low level, and the first transistor T1 is turned on. The first power supply signal ELVDD is written into the first electrode and the second electrode of the driving transistor TD through the first transistor T1 and the driving transistor TD.
It can be understood that in the third reset phase M3, the first light-emitting control module 101 is used to transmit the first power supply signal ELVDD to the first electrode and the second electrode of the driving transistor TD, so that under different data signals Data, the pixel driving circuit 100 can reset the potentials of the first electrode and the second electrode of the driving transistor TD to the same value, reducing the impact on the characteristics of the driving transistor DT.
In the light-emitting phase M4, the light-emitting device D is controlled to emit light by the first light-emitting control module 101 in response to the first enable signal EM_L and by the second light-emitting control module 102 in response to the second enable signal EM_R.
Specifically, in the light-emitting phase M4, both the first enable signal EM_L and the second enable signal EM_R are at a low level, and both the first transistor T1 and the second transistor T2 are turned on. Current flows to the light-emitting device D through the first transistor T1, the driving transistor TD, and the second transistor T2, thereby enabling the light-emitting device D to emit light normally.
In some embodiments of the present application, the pixel driving circuit 100 further includes a second capacitor Cboost. One electrode plate of the second capacitor Cboost is electrically connected to the third node Q. Another electrode plate of the second capacitor Cboost is configured to access the first control signal PScan(n).
The function of the second capacitor Cboost is to adjust the potential of the third node Q, that is, to adjust the potential of the gate of the driving transistor TD. This changes the variation range of different data signals Data and improves the phenomenon of image flicker caused by large leakage current of the display panel.
Please refer to FIG. 3 and FIG. 4. FIG. 4 is a schematic diagram of a signal timing sequence of a writing frame of the pixel driving circuit shown in FIG. 3. The pixel driving circuit 100 shown in FIG. 3 is different from the pixel driving circuit 100 shown in FIG. 1 in that, in embodiments of the present application, the holding frame includes at least one sub-frame, and when the brightness of the writing frame is greater than the brightness of the first sub-frame of the holding frame, then in the first reset phase M1, the first initialization module 105 writes the first initialization signal Vi1 into the fourth node C in response to the third control signal PScan(n-1), and the second light-emitting control module 102 writes the first initialization signal Vi1 into the first electrode and the second electrode of the driving transistor TD in response to the second enable signal EM_R.
Specifically, in the first reset phase M1, both the third control signal PScan(n-1) and the second enable signal EM_R are at a low level, the sixth transistor T6 and the second transistor T2 are turned on, and the first initialization signal Vi1 is written into the first electrode and the second electrode of the driving transistor TD through the sixth transistor T6 and the second transistor T2.
In embodiments of the present application, the writing frame further includes a second reset phase M5, and the second reset phase M5 is presented between the first reset phase M1 and the data writing phase M2.
In the second reset phase M5, the second initialization module 104 writes the second initialization signal Vi2 into the gate of the driving transistor TD in response to the fourth control signal NScan(n), so as to complete the initialization of the gate of the driving transistor TD.
Specifically, in the second reset phase M5, the fourth control signal NScan(n) is at a high level, and the fifth transistor T5 is turned on. The second initialization signal Vi2 is written into the gate of the driving transistor TD through the fifth transistor T5.
It can be understood that writing the first initialization signal Vi1 into the first electrode and the second electrode of the driving transistor TD can make the gate-source voltage Vgs of the driving transistor TD be at a fixed value Vgs=Vgd=Vi2-Vi1. Since the voltage value of the first initialization signal Vi1 is relatively small, the voltage difference of Vgs/Vgd is reduced, that is, the characteristic reset effect of the driving transistor TD is reduced, which can effectively reduce the brightness of the writing frame and improve the flicker caused by the high brightness of the writing frame.
In embodiments of the present application, the first control signal PScan(n) and the third control signal PScan(n-1) are different signals.
It can be understood that when writing the first initialization signal Vi1 into the first electrode and the second electrode of the driving transistor TD in the first reset phase M1, the first initialization module 105 and the second light-emitting control module 102 need to operate simultaneously. The data writing phase M2 is after the first reset phase M1. Therefore, the first control signal PScan(n) and the third control signal PScan(n-1) are different signals, so as to ensure the normal operation of the pixel driving circuit 100.
In embodiments of the present application, the driving timing sequence of the pixel driving circuit 100 further includes a third reset phase M3 and a light-emitting phase M4 after the data writing phase M2, which can be referred to the above embodiments and will not be repeated here.
In embodiments of the present application, in the holding frame, the data writing module 103 is further configured to write the data signal Data into the first electrode and the second electrode of the driving transistor TD at least one time.
Specifically, please refer to FIG. 3 and FIG. 5. FIG. 5 is a schematic diagram of signal timing sequences of a writing frame and a holding frame of the pixel driving circuit shown in FIG. 3. The embodiments of the present application are described by taking that the holding frame includes two sub-frames, namely a first sub-frame and a second sub-frame, as an example.
The signal timing sequences of the first sub-frame and the second sub-frame are the same. The difference from the writing frame is that in the first sub-frame or the second sub-frame, the driving timing sequence of the pixel driving circuit 100 does not include the first reset phase M1. Moreover, in the data writing phase M2, the fourth control signal NScan(n) is always maintained at a low level, and both the fourth transistor T4 and the fifth transistor T5 are always turned off. When the first control signal PScan(n) is at a low level, the third transistor T3 is turned on, and the data writing module 103 writes the data signal Data into the first electrode and the second electrode of the driving transistor TD, that is, resets the first electrode and the second electrode of the driving transistor TD. It can be seen that the first electrode and the second electrode of the driving transistor TD are reset in each sub-frame of the holding frame.
In the first sub-frame or the second sub-frame, the gate of the driving transistor TD maintains the data signal Data written in the writing frame. It should be noted that the data signal Data written in the writing frame is different from the data signal Data written in the holding frame.
Please refer to FIG. 6. FIG. 6 is a schematic diagram of a structure of the display panel provided by an embodiment of the present application. Embodiments of the present application further provide a display panel 1000, including a plurality of pixel units 110 arranged in an array. Each pixel unit 110 includes the pixel driving circuit 100 according to any of the above embodiments, which can be referred to the above content and will not be repeated here.
In embodiments of the present application, the display panel 1000 may be an OLED (Organic Light-Emitting Diode) display panel, a Mini LED (Mini Light-Emitting Diode) display panel, a Micro LED (Micro Light-Emitting Diode) display panel, or the like.
In the display panel 1000 provided by embodiments of the present application, the pixel driving circuit 100 includes a first light-emitting control module, a driving transistor, a second light-emitting control module, a data writing module, a second initialization module, a first initialization module, a first capacitor, and a light-emitting device. In embodiments of the present application, before the data writing phase, the first power supply signal or the first initialization signal is written into the first electrode and the second electrode of the driving transistor in the first reset phase, so that the reset effect of the driving transistor in the writing frame can be adjusted by changing the gate-source voltage of the driving transistor, the difference in the characteristic reset effect of the driving transistor between the writing frame and the holding frame can be reduced, further the brightness difference of the display panel between the writing frame and the holding frame can be reduced, and image flicker can be improved.
The above describes the pixel driving circuit and the display panel provided by the embodiments of the present application. The above description is only used to help understand the method and the core idea of the present application. The present application may have other various embodiments. Without departing from the spirit and essential points of the present application, those skilled in the art can make various corresponding changes and modifications according to the present application, but these corresponding changes and modifications shall all fall within the protection scope of the appended claims of the present application.

Claims

A pixel driving circuit, comprising:
a driving transistor;

a first light-emitting control module, wherein a control terminal of the first light-emitting control module is configured to access a first enable signal, an input terminal of the first light-emitting control module is configured to access a first power supply signal, and an output terminal of the first light-emitting control module is electrically connected to a first electrode of the driving transistor;

a second light-emitting control module, wherein a control terminal of the second light-emitting control module is configured to access a second enable signal, and an output terminal of the second light-emitting control module is electrically connected to a second electrode of the driving transistor;

a data writing module, wherein a first control terminal of the data writing module is configured to access a first control signal, a second control terminal of the data writing module is configured to access a second control signal, an input terminal of the data writing module is configured to access a data signal, wherein the data writing module is further electrically connected to a gate, the first electrode, and the second electrode of the driving transistor; and

a first initialization module, wherein a control terminal of the first initialization module is configured to access a third control signal, an input terminal of the first initialization module is configured to access a first initialization signal, and an output terminal of the first initialization module is electrically connected to an input terminal of the second light-emitting control module;

wherein a driving timing sequence of the pixel driving circuit comprises a writing frame and a holding frame, and the writing frame comprises a first reset phase and a data writing phase performed in sequence; wherein in the first reset phase, the first light-emitting control module is configured to write the first power supply signal into the first electrode and the second electrode of the driving transistor, or the first initialization module and the second light-emitting control module are configured to write the first initialization signal into the first electrode and the second electrode of the driving transistor.
The pixel driving circuit according to claim 1, wherein the holding frame comprises at least one sub-frame; and when brightness of the writing frame is less than brightness of the first sub-frame of the holding frame, the first power supply signal is written into the first electrode and the second electrode of the driving transistor in the first reset phase by the first light-emitting control module in response to the first enable signal.
The pixel driving circuit according to claim 2, wherein the first control signal and the third control signal are the same signal.
The pixel driving circuit according to claim 2, further comprising a second initialization module, wherein a control terminal of the second initialization module is configured to access a fourth control signal, an input terminal of the second initialization module is configured to access a second initialization signal, and an output terminal of the second initialization module is electrically connected to the gate of the driving transistor;
wherein in the first reset phase, the second initialization module writes the second initialization signal into the gate of the driving transistor in response to the fourth control signal.
The pixel driving circuit according to claim 4, wherein the second initialization module comprises a fifth transistor, wherein a gate of the fifth transistor is configured to access the fourth control signal, one of a source and a drain of the fifth transistor is configured to access the second initialization signal, and another of the source and the drain of the fifth transistor is electrically connected to the gate of the driving transistor.
The pixel driving circuit according to claim 5, wherein the fifth transistor is an N-type oxide transistor.
The pixel driving circuit according to claim 1, wherein the holding frame comprises at least one sub-frame; and when brightness of the writing frame is greater than brightness of a first sub-frame of the holding frame, the first initialization signal is written into the first electrode and the second electrode of the driving transistor in the first reset phase by the first initialization module in response to the third control signal and by the second light-emitting control module in response to the second enable signal.
The pixel driving circuit according to claim 7, further comprising a second initialization module, wherein a control terminal of the second initialization module is configured to access a fourth control signal, an input terminal of the second initialization module is configured to access a second initialization signal, and an output terminal of the second initialization module is electrically connected to the gate of the driving transistor;
wherein the writing frame further comprises a second reset phase, and the second reset phase is presented between the first reset phase and the data writing phase;

wherein in the second reset phase, the second initialization module writes the second initialization signal into the gate of the driving transistor in response to the fourth control signal.
The pixel driving circuit according to claim 7, wherein the first control signal and the third control signal are different signals.
The pixel driving circuit according to claim 1, wherein the first light-emitting control module comprises a first transistor, wherein a gate of the first transistor is configured to access the first enable signal, one of a source and a drain of the first transistor is configured to access the first power supply signal, and another of the source and the drain of the first transistor is electrically connected to the first electrode of the driving transistor.
The pixel driving circuit according to claim 1, wherein the second light-emitting control module comprises a second transistor, wherein a gate of the second transistor is configured to access the second enable signal, one of a source and a drain of the second transistor is electrically connected to the second electrode of the driving transistor, and another of the source and the drain of the second transistor is electrically connected to the first initialization module.
The pixel driving circuit according to claim 1, wherein the data writing module comprises a third transistor and a fourth transistor, wherein a gate of the third transistor is configured to access the first control signal, one of a source and a drain of the third transistor is configured to access the data signal, another of the source and the drain of the third transistor is electrically connected to the first electrode of the driving transistor, a gate of the fourth transistor is configured to access the second control signal, one of the source and the drain of the fourth transistor is electrically connected to the second electrode of the driving transistor, and another of the source and the drain of the fourth transistor is electrically connected to the gate of the driving transistor.
The pixel driving circuit according to claim 1, wherein the first initialization module comprises a sixth transistor, wherein a gate of the sixth transistor is configured to access the third control signal, one of a source and a drain of the sixth transistor is configured to access the first initialization signal, and another of the source and the drain of the sixth transistor is electrically connected to the second light-emitting control module.
The pixel driving circuit according to claim 1, further comprising a first capacitor, wherein one electrode plate of the first capacitor is electrically connected to the gate of the driving transistor, and another electrode plate of the first capacitor is configured to access the first power supply signal.
The pixel driving circuit according to claim 1, further comprising a second capacitor, wherein one electrode plate of the second capacitor is electrically connected to the gate of the driving transistor, and another electrode plate of the second capacitor is configured to access the first control signal.
The pixel driving circuit according to claim 1, wherein the first light-emitting control module comprises a first transistor, wherein a gate of the first transistor is configured to access the first enable signal, one of a source and a drain of the first transistor is configured to access the first power supply signal, and another of the source and the drain of the first transistor is electrically connected to the first electrode of the driving transistor;
the second light-emitting control module comprises a second transistor, wherein a gate of the second transistor is configured to access the second enable signal, and one of a source and a drain of the second transistor is electrically connected to the second electrode of the driving transistor;

the data writing module comprises a third transistor and a fourth transistor, wherein a gate of the third transistor is configured to access the first control signal, one of a source and a drain of the third transistor is configured to access the data signal, another of the source and the drain of the third transistor is electrically connected to the first electrode of the driving transistor, a gate of the fourth transistor is configured to access the second control signal, one of the source and the drain of the fourth transistor is electrically connected to the gate of the driving transistor, and another of the source and the drain of the fourth transistor is electrically connected to the second electrode of the driving transistor;

the first initialization module comprises a sixth transistor, wherein a gate of the sixth transistor is configured to access the third control signal, one of a source and a drain of the sixth transistor is configured to access the first initialization signal, and another of the source and the drain of the sixth transistor is electrically connected to another of the source and the drain of the second transistor; and

the first transistor, the driving transistor, the second transistor, the third transistor, and the sixth transistor are P-type low-temperature polysilicon transistors, and the fourth transistor is an N-type oxide transistor.
The pixel driving circuit according to claim 1, wherein the driving timing sequence of the pixel driving circuit further comprises a third reset phase and a light-emitting phase after the data writing phase;
in the data writing phase, the data writing module transmits the compensated data signal to the gate of the driving transistor in response to the first control signal and the second control signal;

in the third reset phase, the first light-emitting control module writes the first power supply signal into the first electrode and the second electrode of the driving transistor in response to the first enable signal; and

in the light-emitting phase, a light-emitting device is controlled to emit light by the first light-emitting control module in response to the first enable signal and by the second light-emitting control module in response to the second enable signal.
The pixel driving circuit according to claim 1, wherein in the holding frame, the data writing module is further configured to write the data signal into the first electrode and the second electrode of the driving transistor at least one time.
A display panel, comprising a plurality of pixel units arranged in an array, and the pixel units comprise the pixel driving circuit according to claim 1.