EP4690461A1

EP4690461A1 - Voltage switching in a power management integrated circuit

Info

Publication number: EP4690461A1
Application number: EP24719933.4A
Authority: EP
Inventors: Robert Moehrke; Nadim Khlat; Michael R. Kay
Original assignee: Qorvo US Inc
Current assignee: Qorvo US Inc
Priority date: 2023-04-03
Filing date: 2024-03-20
Publication date: 2026-02-11
Also published as: WO2024211085A1; KR20250172830A; TW202441908A; CN120917662A

Abstract

Voltage switching in a power management integrated circuit (PMIC) is provided. Herein, the PMIC is required to change a voltage from a present level in a present time interval to a future level in an upcoming time interval with a very short switching interval (e.g., < 2 microseconds). As such, the PMIC is configured to determine a voltage transition scheme based at least on the present level and the future level of the voltage. By determining and employing an appropriate voltage transition scheme, the PMIC can change the voltage from the present level to the future level in a timely manner.

Description

VOLTAGE SWITCHING IN A POWER MANAGEMENT INTEGRATED CIRCUIT

Related Applications

[0001] This application claims the benefit of U.S. provisional patent application serial number 63/456,661 , filed on April 3, 2023, the disclosure of which is hereby incorporated herein by reference in its entirety.

Field of the Disclosure

[0002] The technology of the disclosure relates generally to a power management integrated circuit (PMIC).

Background

[0003] Fifth generation (5G) new radio (NR) (5G-NR) has been widely regarded as the next generation of wireless communication technology beyond the current third generation (3G) and fourth generation (4G) technologies. In this regard, a wireless communication device capable of supporting the 5G-NR wireless communication technology is expected to achieve higher data rates, improved coverage range, enhanced signaling efficiency, and reduced latency. [0004] Downlink and uplink transmissions in a 5G-NR system are widely based on orthogonal frequency division multiplexing (OFDM) technology. In an OFDM based system, physical radio resources are divided into a number of subcarriers in a frequency domain and a number of OFDM symbols in a time domain. The subcarriers are orthogonally separated from each other by a subcarrier spacing (SOS). The OFDM symbols are separated from each other by a cyclic prefix (CP), which acts as a guard band to help overcome inter-symbol interference (ISI) between the OFDM symbols.

[0005] A radio frequency (RF) signal communicated in the OFDM based system is often modulated into multiple subcarriers in the frequency domain and multiple OFDM symbols in the time domain. The multiple subcarriers occupied by the RF signal collectively define a modulation bandwidth of the RF signal. The multiple OFDM symbols, on the other hand, define multiple time intervals during which the RF signal is communicated. In the 5G-NR system, the RF signal is typically modulated with a high modulation bandwidth in excess of 200 MHz.

[0006] The duration of an OFDM symbol depends on the SCS and the modulation bandwidth. The table below (Table 1 ) provides some OFDM symbol durations, as defined by 3G partnership project (3GPP) standards for various SCSs and modulation bandwidths. Notably, the higher the modulation bandwidth is, the shorter the OFDM symbol duration will be. For example, when the SCS is 120 KHz and the modulation bandwidth is 400 MHz, the OFDM symbol duration is 8.93 ps.

Table 1

[0007] In a 5G-NR system, the RF signal can be modulated with a timevariant power that changes from one OFDM symbol to another. In this regard, a power amplifier circuit(s) is required to amplify the RF signal to a certain power level within each OFDM symbol duration. Such inter-symbol power variation creates a unique challenge for a power management integrated circuit (PMIC) because the PMIC must be able to adapt a voltage supplied to the power amplifier circuit within the CP of each OFDM symbol to help avoid distortion (e.g., amplitude clipping) in the RF signal.

Summary

[0008] Embodiments of the disclosure relate to voltage switching in a power management integrated circuit (PMIC). Herein, the PMIC is required to change a voltage from a present level in a present time interval to a future level in an upcoming time interval with a very short switching interval (e.g., < 2 microseconds). As such, the PMIC is configured to determine a voltage transition scheme based at least on the present level and the future level of the voltage. By determining and employing an appropriate voltage transition scheme, the PMIC can change the voltage from the present level to the future level in a timely manner.

[0009] In one aspect, a PMIC is provided. The PMIC includes a voltage processing circuit. The voltage processing circuit is configured to generate a voltage in each of multiple time intervals for amplifying a radio frequency (RF) signal. The PMIC also includes a control circuit. The control circuit is configured to receive a target voltage indicating a future level of the voltage in an upcoming time interval among the multiple time intervals. The control circuit is also configured to determine a present level of the voltage in a present time interval immediately preceding the upcoming time interval among the multiple time intervals. The control circuit is also configured to select a voltage transition scheme based at least on the present level of the voltage, the future level of the voltage, and a threshold voltage. The control circuit is also configured to control the voltage processing circuit to transition the voltage from the present level to the future level based on the selected voltage transition scheme.

[0010] In another aspect, a method for switching a voltage in a PMIC is provided. The method includes receiving a target voltage indicating a future level of the voltage in an upcoming time interval among multiple time intervals. The method also includes determining a present level of the voltage in a present time interval immediately preceding the upcoming time interval among the multiple time intervals. The method also includes selecting a voltage transition scheme based at least on the present level of the voltage, the future level of the voltage, and a threshold voltage. The method also includes transitioning the voltage from the present level to the future level based on the selected voltage transition scheme.

[0011] In another aspect, a wireless device is provided. The wireless device includes a PMIC. The PMIC includes a voltage processing circuit. The voltage processing circuit is configured to generate a voltage in each of multiple time intervals for amplifying a radio frequency (RF) signal. The PMIC also includes a control circuit. The control circuit is configured to receive a target voltage indicating a future level of the voltage in an upcoming time interval among the multiple time intervals. The control circuit is also configured to determine a present level of the voltage in a present time interval immediately preceding the upcoming time interval among the multiple time intervals. The control circuit is also configured to select a voltage transition scheme based at least on the present level of the voltage, the future level of the voltage, and a threshold voltage. The control circuit is also configured to control the voltage processing circuit to transition the voltage from the present level to the future level based on the selected voltage transition scheme.

[0012] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.

Brief Description of the Drawing Figures

[0013] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0014] Figure 1 is a schematic diagram of an exemplary wireless communication circuit wherein a power management integrated circuit (PMIC) is configured according to embodiments of the present disclosure to change a voltage based on a selected voltage transition scheme;

[0015] Figure 2 is a flowchart of an exemplary process whereby the PMIC in Figure 1 can determine the selected voltage transition scheme;

[0016] Figure 3 is a schematic diagram of a control circuit in the PMIC in Figure 1 ; [0017] Figure 4 is a schematic diagram of an exemplary communication device wherein the wireless communication circuit of Figure 1 can be provided; and

[0018] Figure 5 is a flowchart of an exemplary process for switching the voltage in the PMIC in Figure 1 .

Detailed Description

[0019] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0020] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. [0021] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being "over" or extending "over" another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly over" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0022] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including" when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0024] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0025] Embodiments of the disclosure relate to voltage switching in a power management integrated circuit (PMIC). Herein, the PMIC is required to change a voltage from a present level in a present time interval to a future level in an upcoming time interval with a very short switching interval (e.g., < 2 microseconds). As such, the PMIC is configured to determine a voltage transition scheme based at least on the present level and the future level of the voltage. By determining and employing an appropriate voltage transition scheme, the PMIC can change voltage from the present level to the future level in a timely manner.

[0026] Figure 1 is a schematic diagram of an exemplary wireless communication circuit 10 wherein a PMIC 12 is configured according to embodiments of the present disclosure to change a voltage Vcc based on a voltage transition scheme selected among a first voltage transition scheme and a second voltage transition scheme. The PMIC 12 includes a voltage output 14 that outputs the voltage Vcc to a power amplifier circuit 16, which is configured to amplify a radio frequency (RF) signal 18 based on the voltage Vcc.

[0027] The RF signal 18, which may be generated by a transceiver circuit 20, is modulated in multiple time intervals. For the sake of reference and illustration, the time intervals are represented hereinafter by a pair of adjacent time intervals SN-I , S , wherein SN immediately succeeds SN-I . Understandably, the RF signal 18 can be modulated in an infinite number of continuous time intervals.

Hereinafter, the time interval SN-I is referred to interchangeably as a present time interval SN-I and the time interval SN is referred interchangeably as an upcoming time interval SN.

[0028] In the context of the present disclosure, each of the time intervals S -I , SN can have a duration of an orthogonal frequency division multiplexing (OFDM) symbol. In this regard, each of the time intervals SN-I , SN has a respective cyclic prefix (CP) that corresponds to a respective sub-carrier spacing (SCS), as shown above in Table 1 . Understandably, each of the time intervals SN-I , SN can be modulated to carry a data payload and/or a reference signal, such as a demodulation reference signal (DMRS) and a sounding reference signal (SRS).

[0029] The PMIC 12 includes a voltage processing circuit 22 that is coupled to the voltage output 14. The voltage processing circuit 22 is configured to generate the voltage Vcc at a respective level in each of the time intervals SN-I , SN. Given that the power amplifier circuit 16 needs to amplify the data symbols and the reference symbols to different power levels, the voltage processing circuit 22 needs to adapt (increase or decrease) the voltage Vcc on a per-symbol basis. Moreover, the voltage processing circuit 22 must change the voltage Vcc from a present level of the voltage Vcc (denoted as “VCC( -I >”) in the present time interval SN-I to a future level of the voltage Vcc (denoted as “VCC(N>”) in the upcoming time interval SN within the respective CP of the upcoming time interval SN.

[0030] In this regard, the PMIC 12 is configured to further include a control circuit 24. The control circuit 24 is configured to dynamically determine whether to change the voltage Vcc based on the first voltage transition scheme or the second voltage transition scheme. As described in detail below, either one of the voltage transition schemes allows the PMIC 12 to adapt the voltage Vcc from the present level VCC(N-I) to the future level VCC( > within a defined voltage transition interval. Herein, the defined voltage transition interval can be two microseconds (2 /zs) or a duration of the respective CP in the upcoming time interval SN, whichever is shorter.

[0031] In an embodiment, the control circuit 24 is configured to receive a target voltage VTGT from the transceiver circuit 20. In a non-limiting example, the control circuit 24 can receive the voltage VTGT via an RF frontend (RFFE) bus 26. Specifically, the target voltage VTGT provides an indication as to how the voltage Vcc will transition (increase, decrease, or remain unchanged) from the present level Vcc(N-i) in the present time interval S -I to the future level VCC< ) in the upcoming time interval SN. In an embodiment, the transceiver circuit 20 may also indicate an end of the present time interval SN-I and/or a start of the upcoming time interval SN. In an alternative embodiment, the control circuit 24 may determine the end of the present time interval SN-I and/or the start of the upcoming time interval SN based on an internal clock and/or information (e.g., SCS) prestored in the control circuit 24. [0032] Accordingly, the control circuit 24 can select one of the first voltage transition scheme and the second voltage transition scheme and control the voltage processing circuit 22 to transition the voltage Vcc from the present level Vcc(N-i) to the future level VCC based on the selected voltage transition scheme. [0033] In an embodiment, the control circuit 24 can determine whether the voltage Vcc should be changed according to the first voltage transition scheme, or the second voltage transition scheme based on a process. In this regard, Figure 2 is a flowchart of an exemplary process 100 whereby the PMIC 12 in Figure 1 can determine whether to change the voltage Vcc based on the first voltage transition scheme or the second voltage transition scheme.

[0034] Herein, the control circuit 24 compares both the present level VCC<N-I) in the present time interval SN-I and the future level VCC<N) in the upcoming time interval SN against a threshold voltage VTH (step 102). If the present level VCC<N-I) and the future level VCC are both higher than or equal to the threshold voltage VTH (VCC(N-I) > VTH and VCC(N> > VTH), or if the present level VCC(N-I) and the future level Vcc(N) are both lower than the threshold voltage VTH (VCC(N-I) < VTH and Vcc(N) < VTH), the control circuit 24 will change the voltage Vcc based on the first voltage transition scheme (step 104). Otherwise, the control circuit 24 will change the voltage Vcc based on the second voltage transition scheme (step 106). Notably, both the first voltage transition scheme and the second voltage transition scheme are so determined to ensure that the PMIC 12 can change the modulated voltage Vcc from the present voltage level VCC<N-I) to the future voltage level VCC within a very short switching interval (e.g., < 20 nanoseconds).

[0035] With reference back to Figure 1 , the voltage processing circuit 22 includes a voltage amplifier 28 (denoted as “VA”), an offset circuit 30, a switcher circuit 32, and a supply voltage circuit 34. The voltage amplifier 28 is coupled to an input 36 of the offset circuit 30 and the offset circuit 30 is coupled to the voltage output 14. In the context of the present disclosure, the power amplifier circuit 16 is assumed to have a much higher bandwidth than that of the offset circuit 30. [0036] Specifically, the voltage amplifier 28 is configured to generate an initial voltage VAMP based on an amplifier target voltage VTGT-AMP and a supply voltage VSUP. The supply voltage circuit 34 is configured to generate the supply voltage VSUP based on a supply target voltage VTGT-SUP and provide the supply voltage VSUP to the voltage amplifier 28.

[0037] The offset circuit 30 includes an offset capacitor GOFF and a bypass switch SBYP. The offset capacitor COFF is coupled between the input 36 and the voltage output 14, and the bypass switch SBYP is coupled between the input 36 and a ground (GND). The offset capacitor GOFF may be charged or discharged to provide an offset voltage VOFF between the voltage amplifier 28 and the voltage output 14. As a result, the offset circuit 30 can raise the initial voltage VAMP by the offset voltage VOFF to thereby generate the voltage Vcc at the voltage output 14 (Vcc = VAMP + VOFF). The voltage processing circuit 22 further includes a feedback loop 38, which is configured to provide a feedback of the voltage Vcc (denoted as “Vcc FB”) at the voltage output 14 to the voltage amplifier 28.

[0038] Under the first voltage transition scheme, the control circuit 24 is configured to cause the offset voltage VOFF to be kept constant in the upcoming time interval SN. Understandably, by keeping the offset voltage VOFF constant, it is not necessary to charge or discharge the offset capacitor GOFF. AS a result, it is possible to prevent potential power loss resulting from charging or discharging the offset capacitor GOFF.

[0039] Alternatively, under the second voltage transition scheme, the control circuit 24 is configured to cause the offset voltage VOFF to be modulated in the upcoming time interval SN. For an in-depth description as to how the control circuit 24 maintains the offset voltage VOFF under the first voltage transition scheme or modulates the offset voltage VOFF under the second voltage transition scheme, please refer to International Patent Application Number PCT/US2023/027865, entitled “VOLTAGE SWITCHING IN A POWER MANAGEMENT INTEGRATED CIRCUIT.”

[0040] The switcher circuit 32 includes a multi-level charge pump (MCP) 40. The MCP 40, which may be a direct current (DC)-DC buck-boost converter, is configured to generate a low-frequency voltage VDC (e.g., DC voltage) based on a battery voltage VBAT. Specifically, the MCP 40 may operate in a buck mode to generate the low-frequency voltage VDC at OXVBAT or 1 XVBAT, or in a boost mode to generate the low-frequency voltage DC at 2XVBAT. The MCP 40 may be configured to toggle between the buck mode and the boost mode based on a duty cycle signal 42 (e.g., 20%@0XVBAT, 30%@1 XVBAT, and 50%@2XVBAT). Accordingly, the MCP 40 may be controlled by the duty cycle signal 42 to generate the low-frequency voltage VDC at any desired level.

[0041] The switcher circuit 32 also includes a power inductor LP coupled in series to the MCP 40. The power inductor Lp is configured to induce a low- frequency current IDC (e.g., a DC current) based on the low-frequency voltage VDC. Given that the duty cycle signal 42 can directly control the low-frequency voltage VDC, the duty cycle signal 42 can likewise cause the low-frequency current IDC to be generated at any desired amount.

[0042] As mentioned earlier, the voltage Vcc at the voltage output 14 is determined by the initial voltage VAMP and the offset voltage VOFF. In this regard, it is possible to change the voltage Vcc by increasing or decreasing the offset voltage VOFF, either in addition to or alternative to changing the initial voltage VAMP. Specifically, to increase the offset voltage VOFF, the control circuit 24 may close the bypass switch SBYP such that the low-frequency current IDC can charge the offset capacitor GOFF to the offset voltage VOFF. TO decrease the offset voltage VOFF, the control circuit 24 can lower the low-frequency voltage VDC such that the offset capacitor COFF can be discharged through the power inductor Lp to decrease the offset voltage VOFF.

[0043] In an embodiment, the voltage amplifier 28 may also source or sink a high-frequency current IAC (e.g., an alternating current) to help speed up charging or discharging of the offset capacitor GOFF. Accordingly, the voltage amplifier 28 is configured to generate a sense current ISENSE to indicate an amount of the high-frequency current IAC that is sourced or sunk by the voltage amplifier 28. As described below, the sense current ISENSE can be utilized to determine the duty cycle signal 42 to help provide a desired amount of the low-frequency current IDC. [0044] In an embodiment, the control circuit 24 is configured to receive the feedback VCC-FB of the voltage Vcc, the initial voltage VAMP, and the sense current ISENSE. Accordingly, the control circuit 24 can determine the amplifier target voltage VTGT-AMP, the supply target voltage VTGT-SUP, and the duty cycle signal 42 to thereby cause the voltage processing circuit 22 to transition the voltage Vcc from the present level VCC(N-I) to the future level VCC within the defined voltage transition interval.

[0045] Figure 3 is a schematic diagram providing an exemplary illustration of the control circuit 24 in Figure 1 . Common elements between Figures 1 and 3 are shown therein with common element numbers and will not be re-described herein.

[0046] Herein, the control circuit 24 includes a common controller 44 (e.g., a microprocessor, a microcontroller, etc.), a memory circuit 46 (e.g., a flash memory, a register bank, etc.), an operational amplifier 48, and a pulse-width modulation (PWM) modulator 50. The common controller 44 can be configured to receive the target voltage VTGT from the transceiver circuit 20 in Figure 1 . The common controller 44 can be further configured to receive the feedback VCC-FB of the voltage Vcc and the feedback of the initial voltage VAMP. Accordingly, the common controller 44 can determine whether to employ the first voltage transition scheme or the second voltage transition scheme in accordance with the process 100 of Figure 2.

[0047] The operational amplifier 48 includes a non-inverted input terminal (denoted as “+”), an inverted input terminal (denoted as “-”), and an output terminal 52. The output terminal 52 may be coupled to the PWM modulator 50, either directly or via a voltage divider circuit 54. As further discussed below, the operational amplifier 48 outputs one-half of the target voltage VTGT (denoted as “¹/₂VTGT”), which indicates the future level VCC(N> of the voltage Vcc in the upcoming time interval SN, to the PWM modulator 50 to thereby change the duty cycle signal 42 generated by the PWM modulator 50.

[0048] The common controller 44 may be coupled directly to the non-inverted input terminal (“+”), and to the inverted input terminal (“-”) of the operational amplifier 48 via an input circuit 56. The input circuit 56 includes a capacitor C3 and a resistor R3 coupled in parallel to each other. In addition, the control circuit 24 also includes a feedback circuit 57 coupled between the inverted terminal and the output terminal 52. The feedback circuit 57 may include a capacitor C1 and a resistor R2 coupled in series between the inverted terminal and the output terminal 52 of the operational amplifier 48 and a capacitor C2 coupled between the inverted terminal and the output terminal 52, in parallel to the capacitor C1 and the resistor R2. The control circuit 24 may also include a switch S1 coupled in parallel to the capacitor C1 . Understandably, when the switch S1 is closed, the capacitor C1 is bypassed.

[0049] In an embodiment, the control circuit 24 further includes an assisting circuit 58. The assisting circuit 58 includes a current source 60 coupled in series with a switch S2 and a resistor R1 . The switch S2 and the resistor R1 are coupled between the inverted terminal and the output terminal 52 of the operational amplifier 48, in parallel to the feedback circuit 57. The assisting circuit 58 can be activated by closing the switch S2 and deactivated by opening the switch S2. When the assisting circuit 58 is activated, the current source 60 can cause an assistance current IASST to flow through the resistor R1 to thereby accelerate a change (increase or decrease) of the target voltage WTGT outputted by the operational amplifier 48.

[0050] The voltage divider circuit 54 can be controlled via switches S3, S4. Specifically, the switch S3 can be closed to couple the sense current ISENSE through the voltage divider circuit 54 or opened to decouple the sense current ISENSE from the voltage divider circuit 54. In an embodiment, the common controller 44 may control the PWM modulator 50, the current source 60, and the switches S1 , S2, S3, S4, either individually or collectively, via at least one control signal 62. In this regard, the common controller 44 can activate or deactivate the assisting circuit 58 via the control signal 62.

[0051] The memory circuit 46 may be preconfigured to store, among others, the threshold voltage VTH and a set of offset target voltages VTGT-OFFI , VTGT-OFF2. In a non-limiting example, the offset target voltages VTGT-OFFI , VTGT-OFF2 can be expressed by equations (Eq. 1.1 and 1.2) below.

VTGT-OFFI = VCC-MIN - VNHEAD (Eq. 1 -1 ) VTGT-OFF2 = VTH - VNHEAD (Eq- 1.2)

[0052] In the equations (Eq. 1 .1 and 1 .2), VCC-MIN represents a minimum level of the voltage Vcc across the present time interval SN-1 and the upcoming time interval SN, VTH represents the threshold voltage, and VNHEAD represents a headroom voltage. Herein, the common controller 44 is configured to determine an offset target voltage VTGT-OFF for the upcoming time interval SN by selecting one of the offset target voltages VTGT-OFFI , VTGT-OFF2 from the memory circuit 46 (VTGT-OFF e (VTGT-OFFI , VTGT-OFF2)). Understandably, by selecting an appropriate one of the offset target voltages VTGT-OFFI , VTGT-OFF2, the control circuit 24 can determine the duty cycle signal 42 to thereby cause the switcher circuit 32 to generate the low-frequency current IDC at the desired level. According to an embodiment of the present disclosure, the common controller 44 can select VTGT- OFFI as the offset target voltage VTGT-OFF (VTGT-OFF = VTGT-OFFI ) when the future level Vcc(N) of the voltage Vcc in the upcoming time interval S is lower than the threshold voltage VTH (VCC<N) < VTH). In contrast, when the future level VCC<N) of the voltage Vcc in the upcoming time interval SN is higher than or equal to the threshold voltage VTH (VCC<N) > VTH), the common controller 44 can select VTGT- OFF2 as the offset target voltage VTGT-OFF (VTGT-OFF = VTGT-OFF2).

[0053] Upon selecting the offset target voltage VTGT-OFF among the offset target voltages VTGT-OFFI , VTGT-OFF2, the common controller 44 is configured to provide one-half of the selected offset target voltage VTGT-OFF (denoted as “ WTGT-OFF”) to the non-inverted terminal (“+”) of the operational amplifier 48. [0054] The common controller 44 also determines the offset voltage VOFF in the present time interval SN-1 based on the feedback VCC-FB of the voltage Vcc and the feedback of the initial voltage VAMP in the present time interval SN-1 (VOFF = VCC-FB - VAMP). Accordingly, the common controller 44 provides one-half of the offset voltage VOFF in the present time interval SN-I (denoted as “ OFF”) to the inverted terminal of the operational amplifier 48 via the input circuit 56. The operational amplifier 48, in turn, outputs the target voltage WTGT to indicate the future level VCC<N) of the voltage Vcc in the upcoming time interval SN.

[0055] As mentioned earlier in Figure 1 , the voltage amplifier 28 may source or sink the high-frequency current IAC to help speed up charging or discharging of the offset capacitor COFF. Understanding that the voltage amplifier 28 may suffer a reduced efficiency when sourcing or sinking the high-frequency current IAC, it is thus desirable to reduce the high-frequency current IAC to help improve the efficiency of the voltage amplifier 28.

[0056] In this regard, the control circuit 24 is further configured to adapt the duty cycle signal 42 in accordance with the high-frequency current IAC being sourced or sunk by the voltage amplifier 28. More specifically, during transition of the voltage Vcc, the common controller 44 can close the switch S3 and open the switch S4 to couple the sense current ISENSE, which serves as an indication of the high-frequency current IAC, into the voltage divider circuit 54 to thereby establish a PWM target voltage VPWM. Accordingly, the PWM modulator 50 can generate the duty cycle signal 42 based on the PWM target voltage VPWM. AS a result, it is possible to increase or decrease the low-frequency current IDC to compensate for the high-frequency current IAC being sourced or sunk by the voltage amplifier 28 to thereby improve efficiency of the voltage amplifier 28.

Accordingly, the PWM target voltage VPWM as received by the PWM modulator 50 can be expressed in equation (Eq. 2.1 ) below. In contrast, outside the transition of the voltage Vcc, the common controller 44 can close the switch S4 and open the switch S3 to thereby cause the PWM target voltage VPWM to be generated in accordance with equation (Eq. 2.2) below.

VPWM = VZVTGT ± ISENSEX2R (Eq. 2.1 )

VPWM = ¹/ZVTGT (Eq- 2.2) [0057] In an embodiment, in the first voltage transition scheme, the common controller 44 is configured to activate the assisting circuit 58 at a start of the upcoming time interval SN and deactivate the assisting circuit 58 at an end of the defined voltage transition interval. As mentioned earlier, the defined voltage transition interval can be a shorter one of 2 /is and the duration of the CP in the upcoming time interval SN. Herein, the common controller 44 can further control the current source 60 to adapt the assistance current IASST to accelerate the transition (increase or decrease) of the offset voltage VOFF, such that the PMIC 12 in Figure 1 can change the voltage Vcc within the defined voltage transition interval.

[0058] In one example, if the defined voltage transition interval is 2 /is, the common controller 44 may control the current source 60 to generate the assistance current IASST as expressed in equation (Eq. 3) below.

IASST = (¹/ZVTGT — ZVOFF) I R1 (Eq. 3)

[0059] In another example, if the defined voltage transition interval is far less than 2 /is (e.g., 0.59 /is associated with 120KHz SCS), the common controller 44 may control the current source 60 to increase the assistance current IASST as expressed in equation (Eq. 4) below.

IASST = (¹/ZVTGT - VZVOFF) / R1 + ( ZVTGT - ¹/2Vcc(N-i)) I R2 (Eq. 4)

[0060] The common controller 44 may close the switch S1 to bypass the capacitor C1 when VTGT is less than one volt (VTGT < 1 V). The common controller 44 may also close the switch S1 to bypass the capacitor C1 to cause the target voltage ¹/ZVTGT at the output terminal 52 to decrease quickly under the follow condition:

Vcc(N-i) - Vcc(N) > 2.5V and VTGT < (VOFF + 0.6V) [0061] In an embodiment, the common controller 44 may also increase an operating frequency of the PWM modulator 50 such that the PWM modulator 50 can make a timely decision as to how the duty cycle signal 42 should be generated. The common controller 44 is further configured to provide the target voltage VTGT to a voltage digital-to-analog converter (VDAC) 64, which will generate the amplifier target voltage VTGT-AMP.

[0062] The common controller 44 is further configured to generate the supply target voltage VTGT-SUP to adapt the supply voltage VSUP. For example, the common controller 44 can decrease the supply target voltage VTGT-SUP to reduce the supply voltage VSUP when the future level Vcc(N) of the voltage Vcc is lower than the present level Vcc(N-i) of the voltage Vcc. The common controller 44 can increase the supply target voltage VTGT-SUP to increase the supply voltage VSUP when the future level VCC<N) of the voltage Vcc is higher than the present level Vcc(N-i) of the voltage Vcc. The common controller 44 can maintain the supply target voltage VTGT SUP at the previous level to keep the supply voltage VSUP unchanged when the future level VCC(NJ of the voltage Vcc is equal to the present level Vcc(N-i) of the voltage Vcc. By adapting the supply voltage VSUP based on the present level VCC(N--I) and the future level VCC(N> of the voltage Vcc, it is possible to improve efficiency and reduce energy waste of the voltage amplifier 28.

[0063] Should the control circuit 24 determine, based on the process 100 of Figure 2, that the PMIC 12 will adapt the voltage Vcc based on the second voltage transition scheme, the control circuit 24 can cause the PMIC 12 to change the voltage Vcc from the present level VCC(N-I) to the future level VCC<N) by modulating the offset voltage VOFF and/or changing only the initial voltage VAMP. [0064] The wireless transmission circuit 10 of Figure 1 can be provided in a communication device to support the embodiments described above. In this regard, Figure 4 is a schematic diagram of an exemplary communication device 100 wherein the wireless transmission circuit 10 of Figure 1 can be provided. [0065] Herein, the communication device 100 can be any type of communication device, such as a mobile terminal, smart watch, tablet, computer, navigation device, access point, base station (e.g., eNB, gNB), and any wireless communication device that supports wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, Ultra-wideband (UWB), and near field communications. The communication device 100 will generally include a control system 102, a baseband processor 104, transmit circuitry 106, receive circuitry 108, antenna switching circuitry 110, multiple antennas 1 12, and user interface circuitry 1 14. In a non-limiting example, the control system 102 can be a field-programmable gate array (FPGA), as an example. In this regard, the control system 102 can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receive circuitry 108 receives radio frequency signals via the antennas 1 12 and through the antenna switching circuitry 110 from one or more base stations. A low noise amplifier and a filter cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using analog-to-digital converter(s) (ADC).

[0066] The baseband processor 104 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations, as will be discussed in greater detail below. The baseband processor 104 is generally implemented in one or more digital signal processors (DSPs) and application specific integrated circuits (ASICs).

[0067] For transmission, the baseband processor 104 receives digitized data, which may represent voice, data, or control information, from the control system 102, which it encodes for transmission. The encoded data is output to the transmit circuitry 106, where a digital-to-analog converter(s) (DAC) converts the digitally encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission, and deliver the modulated carrier signal to the antennas 1 12 through the antenna switching circuitry 110. The multiple antennas 1 12 and the replicated transmit and receive circuitries 106, 108 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0068] In one embodiment, the PMIC 12 may be provided in the antenna switching circuitry 1 10 and coupled to the transmit circuitry 106 and/or the receive circuitry 108. In another embodiment, the PMIC 12 may be a separate circuit provided in between the transmit circuitry 106 and the antenna switching circuitry 1 10. Notably, the PMIC 12 may also be provided in any other circuits in the communication device 100.

[0069] In an embodiment, it is possible to switch the voltage Vcc in the PMIC 12 based on a process. In this regard, Figure 5 is a flowchart of an exemplary process 200 for switching the voltage Vcc in the PMIC 12 in Figure 1 .

[0070] Herein, the process 200 includes receiving the target voltage VTGT indicating the future level VCC( > of the voltage Vcc in the upcoming time interval SN among the time intervals SN-I , SN (step 202). The process 200 also includes determining the present level VCC(N-I) of the voltage Vcc in the present time interval SN-I immediately preceding the upcoming time interval SN among the time intervals S -I , SN (step 204). The process 200 also includes selecting the voltage transition scheme based at least on the present level VCC<N-I) of the voltage Vcc, the future level VCC(NJ of the voltage Vcc, and the threshold voltage VTH (step 206). The process 200 also includes transitioning the voltage Vcc from the present level VCC<N-I) to the future level VCC<N) based on the selected voltage transition scheme (step 208).

[0071] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims

Claims What is claimed is:

1 . A power management integrated circuit, PMIC, (12) comprising: a voltage processing circuit (22) configured to generate a voltage (Vcc) in each of a plurality of time intervals (SN-I , SN) for amplifying a radio frequency, RF, signal (18); and a control circuit (24) configured to: receive a target voltage (VTGT) indicating a future level (VCC(NJ) of the voltage (Vcc) in an upcoming time interval (SN) among the plurality of time intervals (S -I , SN) ; determine a present level (VCC(N-I>) of the voltage (Vcc) in a present time interval (SN-I) immediately preceding the upcoming time interval (S ) among the plurality of time intervals (SN-I , SN) ; select a voltage transition scheme based at least on the present level (Vcc(N-i)) of the voltage (Vcc), the future level (VCC<N)) of the voltage (Vcc), and a threshold voltage (VTH); and control the voltage processing circuit (22) to transition the voltage (Vcc) from the present level (VCC(N-I>) to the future level (Vcc(N)) based on the selected voltage transition scheme.

2. The PMIC (12) of claim 1 , wherein the control circuit (24) is further configured to: control the voltage processing circuit (22) based on a first voltage transition scheme under any of following conditions: the present level (VCC(N-I>) and the future level (VCC<N)) of the voltage (Vcc) are both higher than or equal to the threshold voltage (VTH); and the present level (VCC(N-I>) and the future level (VCC<N)) of the voltage (Vcc) are both lower than the threshold voltage (VTH); and control the voltage processing circuit (22) based on a second voltage transition scheme under any following conditions: the present level (VCC(N-I>) of the voltage (Vcc) is higher than or equal to the threshold voltage (VTH) and the future level (Vcc(N)) of the voltage (Vcc) is lower than the threshold voltage (VTH); and the present level (VCC(N-I>) of the voltage (Vcc) is lower than the threshold voltage (VTH) and the future level (Vcc(N>) of the voltage (Vcc) is higher than or equal to the threshold voltage (VTH).

3. The PMIC (12) of claim 2, wherein the voltage processing circuit (22) comprises: a voltage amplifier (28) configured to generate an initial voltage (VAMP) based on a supply voltage (VSUP) and an amplifier target voltage (VTGT-AMP); an offset circuit (30) configured to raise the initial voltage (VAMP) by an offset voltage (VOFF) to generate the voltage (Vcc); a switcher circuit (32) configured to generate a low-frequency current (IDC) based on a duty cycle signal (42) to thereby cause the offset circuit (30) to provide the offset voltage (VOFF); and a supply voltage circuit (34) configured to generate the supply voltage (VSUP) based on a supply target voltage (VTGT-SUP).

4. The PMIC (12) of claim 3, wherein the control circuit (24) is further configured to: cause the offset circuit (30) to keep the offset voltage (VOFF) constant under the first voltage transition scheme; and cause the offset circuit (30) to modulate the offset voltage (VOFF) under the second voltage transition scheme.

5. The PMIC (12) of claim 3, wherein the control circuit (24) comprises: a pulse-width modulation, PWM, modulator (50) configured to generate the duty cycle signal (42) based on a PWM target voltage (VPWM) that is related to one-half of the target voltage (VTGT) ; an operational amplifier (48) configured to output the one-half of the future level (Vcc(N>) of the voltage (Vcc) based on one-half of an offset target voltage (VTGT-OFF) in the upcoming time interval (SN) and one- half of the offset voltage (VOFF) in the present time interval (SN 1 ); and a common controller (44) configured to: determine the one-half of the offset target voltage (VTGT-OFF) in the upcoming time interval (SN) based on the present level (VCC(N-I>) of the voltage (Vcc), the future level (VCC(N>) of the voltage (Vcc), and the threshold voltage (VTH); and determine the one-half of the offset voltage (VOFF) in the present time interval (SN-I) based on feedback (VCC-FB) of the voltage (Vcc) and the initial voltage (VAMP).

6. The PMIC (12) of claim 5, wherein the common controller (44) is further configured to: determine the offset target voltage (VTGT-OFF) to be equal to (VCC-MI - VNHEAD) when the future level (VCC(N>) of the voltage (Vcc) is lower than the threshold voltage (VTH) ; and determine the offset target voltage (VTGT-OFF) to be equal to (VTH - VNHEAD) when the future level (VCC(N>) of the voltage (Vcc) is higher than or equal to the threshold voltage (VTH) ; wherein VCC-MIN represents a minimum level of the voltage (Vcc); V HEAD represents a headroom voltage; and VTH represents the threshold voltage.

7. The PMIC (12) of claim 5, wherein the control circuit (24) further comprises an assisting circuit (58) and the common controller (44) is further configured to activate the assisting circuit (58) in one or more of the first voltage transition scheme and the second voltage transition scheme to cause the operational amplifier (48) to output the one-half of the future level (VCC(N>) of the voltage (Vcc) within a defined voltage transition interval.

8. The PMIC (12) of claim 7, wherein the common controller is further configured to deactivate the assisting circuit at an end of the defined voltage transition interval.

9. The PMIC (12) of claim 7, wherein the common controller is further configured to: increase the supply target voltage when the future level of the voltage is higher than the present level of the voltage; decrease the supply target voltage when the future level of the voltage is lower than the present level of the voltage; and maintain the supply target voltage when the future level of the voltage is equal to the present level of the voltage.

10. The PMIC (12) of claim 1 , wherein each of the plurality of time intervals has a duration of an orthogonal frequency division multiplexing (OFDM) symbol.

1 1. A method for switching a voltage (Vcc) in a power management integrated circuit, PMIC, (12) comprising: receiving a target voltage (VTGT) indicating a future level (VCC< >) of the voltage (Vcc) in an upcoming time interval (SN) among a plurality of time intervals (S -I , SN); determining a present level (Vcc(N-i)) of the voltage (Vcc) in a present time interval (SN-I) immediately preceding the upcoming time interval (SN) among the plurality of time intervals (SN-I , SN); selecting a voltage transition scheme based at least on the present level (Vcc(N-i)) of the voltage (Vcc), the future level (VCC(N>) of the voltage (Vcc), and a threshold voltage (VTH); and transitioning the voltage (Vcc) from the present level (VCC( -I>) to the future level (Vcc(N>) based on the selected voltage transition scheme.

12. The method of claim 11 , wherein selecting the voltage transition scheme comprises: selecting a first voltage transition scheme under any following conditions: the present level (VCC(N-I>) and the future level (VCC(NJ) of the voltage (Vcc) are both higher than or equal to the threshold voltage (VTH); and the present level (VCC(N-I>) and the future level (VCC(NJ) of the voltage (Vcc) are both lower than the threshold voltage (VTH); and selecting a second voltage transition scheme under any following conditions: the present level (VCC(N-I>) of the voltage (Vcc) is higher than or equal to the threshold voltage (VTH) and the future level (Vcc(N)) of the voltage (Vcc) is lower than the threshold voltage (VTH); and the present level (VCC(N-I>) of the voltage (Vcc) is lower than the threshold voltage (VTH) and the future level (VCC(N>) of the voltage (Vcc) is higher than or equal to the threshold voltage (VTH).

13. A wireless device (100) comprising a power management integrated circuit, PMIC, (12) comprising: a voltage processing circuit (22) configured to generate a voltage (Vcc) in each of a plurality of time intervals (SN-I , SN) for amplifying a radio frequency, RF, signal (18); and a control circuit (24) configured to: receive a target voltage (VTGT) indicating a future level (VCC<N)) of the voltage (Vcc) in an upcoming time interval (SN) among the plurality of time intervals (S -I , SN) ; determine a present level (Vcc(N-i>) of the voltage (Vcc) in a present time interval (SN-I) immediately preceding the upcoming time interval (S ) among the plurality of time intervals (SN-I , SN) ; select a voltage transition scheme based at least on the present level (Vcc(N-i)) of the voltage (Vcc), the future level (VCC(N>) of the voltage (Vcc), and a threshold voltage (VTH); and control the voltage processing circuit (22) to transition the voltage (Vcc) from the present level (VCC(N-I>) to the future level (Vcc(N)) based on the selected voltage transition scheme.

14. The wireless device (100) of claim 12, wherein the control circuit (24) is further configured to: control the voltage processing circuit (22) based on a first voltage transition scheme under any following conditions: the present level (VCC(N-I>) and the future level (VCC<N)) of the voltage (Vcc) are both higher than or equal to the threshold voltage (VTH); and the present level (VCC(N-I>) and the future level (VCC ) of the voltage (Vcc) are both lower than the threshold voltage (VTH); and control the voltage processing circuit (22) based on a second voltage transition scheme under any following conditions: the present level (VCC(N-I>) of the voltage (Vcc) is higher than or equal to the threshold voltage (VTH) and the future level (Vcc(N)) of the voltage (Vcc) is lower than the threshold voltage (VTH); and the present level (VCC(N-I>) of the voltage (Vcc) is lower than the threshold voltage (VTH) and the future level (Vcc(N)) of the voltage (Vcc) is higher than or equal to the threshold voltage (VTH).

15. The wireless device (100) of claim 14, wherein the voltage processing circuit (22) comprises: a voltage amplifier (28) configured to generate an initial voltage (VAMP) based on a supply voltage (VSUP) and an amplifier target voltage (VTGT-AMP); an offset circuit (30) configured to raise the initial voltage (VAMP) by an offset voltage (VOFF) to generate the voltage (Vcc); a switcher circuit (32) configured to generate a low-frequency current (IDO) based on a duty cycle signal (42) to thereby cause the offset circuit (30) to provide the offset voltage (VOFF); and a supply voltage circuit (34) configured to generate the supply voltage (VSUP) based on a supply target voltage (VTGT-SUP).

16. The wireless device (100) of claim 15, wherein the control circuit is further configured to: cause the offset circuit (30) to keep the offset voltage (VOFF) constant under the first voltage transition scheme; and cause the offset circuit (30) to modulate the offset voltage (VOFF) under the second voltage transition scheme.

17. The wireless device (100) of claim 15, wherein the control circuit (24) comprises: a pulse-width modulation, PWM, modulator (50) configured to generate the duty cycle signal (42) based on a PWM target voltage (VPWM) that is related to one-half of the target voltage (VTGT) ; an operational amplifier (48) configured to output the one-half of the future level (Vcc(N>) of the voltage (Vcc) based on one-half of an offset target voltage (VTGT-OFF) in the upcoming time interval (SN) and one- half of the offset voltage (VOFF) in the present time interval (SN-I ); and a common controller (44) configured to: determine the one-half of the offset target voltage (VTGT-OFF) in the upcoming time interval (SN) based on the present level (Vcc(N-i>) of the voltage (Vcc), the future level (VCC(N>) of the voltage (Vcc), and the threshold voltage (VTH); and determine the one-half of the offset voltage (VOFF) in the present time interval (SN-I) based on feedback (Vcc FB) of the voltage (Vcc) and the initial voltage (VAMP).

18. The wireless device (100) of claim 17, wherein the common controller (44) is further configured to: determine the offset target voltage (VTGT-OFF) to be equal to (VCC-MI - V HEAD) when the future level of the voltage is lower than the threshold voltage; and determine the offset target voltage (VTGT-OFF) to be equal to (VTH - VNHEAD) when the future level of the voltage is higher than or equal to the threshold voltage; wherein Vcc MIN represents a minimum level of the voltage; VNHEAD represents a headroom voltage; and VTH represents the threshold voltage.

19. The wireless device (100) of claim 17, wherein the control circuit (24) further comprises an assisting circuit (58) and the common controller (44) is further configured to activate the assisting circuit (58) in one or more of the first voltage transition scheme and the second voltage transition scheme to cause the operational amplifier (48) to output the one-half of the future level (Vcc(N>) of the voltage (Vcc) within a defined voltage transition interval.

20. The wireless device (100) of claim 19, wherein the common controller (44) is further configured to deactivate the assisting circuit (58) at an end of the defined voltage transition interval.