EP4684423A1 - Semiconductor package with top-side heat spreader and bottom-side flat - Google Patents

Abstract

The present disclosure relates to a semiconductor package. The semiconductor package includes a semiconductor die, a plurality of flat leads on a first side of the semiconductor package, and a heat spreader on a second side of the semiconductor package. The plurality of flat leads is electrically connected to the semiconductor die. The heat spreader has a thickness that is at least 1.5 times a thickness of an individual lead of the plurality of leads.

Description

TSLA.755WO PATENT SEMICONDUCTOR PACKAGE DESIGN WITH TOP-SIDE HEAT SPREADER AND BOTTOM-SIDE FLAT LEADS CROSS-REFERENCE TO RELATED APPLICATION [0001] This application claims the benefit of U.S. Provisional Patent Application No. 63/491,500, entitled “SEMICONDUCTOR PACKAGE DESIGN WITH TOP-SIDE HEAT SPREADER AND BOTTOM-SIDE STAMPED FLAT LEADS,” filed on March 21, 2023, the disclosure of which is hereby incorporated by reference in its entirety and for all purposes. BACKGROUND Technical Field [0002] This application relates to semiconductor device packages. In particular, some embodiments relate to semiconductor packages with heat spreaders on one side and flat leads on another side and related methods of manufacture. Description of Related Technology [0003] Semiconductor devices are used in a wide variety of applications. In some applications, semiconductor devices can experience high electrical loads that can result in significant heating of the semiconductor device. There may be technical problems associated with high electrical loads, such as detrimental heating of the semiconductor device from the high load. In addition, conductors providing electrical connections to semiconductor packages can impact cost and performance of the semiconductor packages. SUMMARY [0004] The innovations described in the claims each have several aspects, no single one of which is solely responsible for its desirable attributes. Without limiting the scope of the claims, some prominent features of this disclosure will now be briefly described. [0005] One aspect of the present disclosure is a semiconductor package that includes a semiconductor die, a plurality of flat leads on a first side of the semiconductor package, and a heat spreader on a second side of the semiconductor package. The plurality of flat leads is electrically connected to the semiconductor die. The second side is positioned opposite to the first side, and the heat spreader has a thickness that is at least 1.5 times a thickness of an individual lead of the plurality of leads. [0006] In one embodiment, the heat spreader can occupy more than two-thirds of an area of a surface of the second side. [0007] In one embodiment, the heat spreader can occupy more than 70% of an area of a surface of the second side. [0008] In one embodiment, the thickness of the heat spreader can be at least 2 times the thickness of the individual lead. [0009] In one embodiment, the thickness of the heat spreader can be less than 10 times the thickness of the individual lead. [0010] In one embodiment, the heat spreader can include copper. [0011] In one embodiment, at least one lead of the plurality of leads can include a wettable flank. [0012] In one embodiment, the semiconductor die can include a switch. [0013] In one embodiment, the semiconductor die can include a field effect transistor having a gate, a source, and a drain. In addition, the plurality of flat leads can include a gate lead connected to the gate, a source lead connected to the source, and a drain lead connected to the drain. [0014] In one embodiment, the semiconductor package can include a molding compound enclosing the semiconductor die. Each lead of the plurality of flat leads can extend beyond the molding compound such that the exposed portion of the lead is flat. [0015] Another aspect of the present disclosure is a semiconductor package that includes a molding compound, a semiconductor die, a plurality of flat leads on a first side of the semiconductor package, and a die paddle on a second side of the semiconductor package. A semiconductor die can include a field effect transistor having a source, a gate, and a drain. The semiconductor die is enclosed by the molding compound. The plurality of flat leads includes a source lead connected to the source, a gate lead connected to the gate, and a drain lead connected to the drain, and each flat lead extends outside of the molding compound. The second side is positioned opposite the first side. The die paddle has a thickness that is at least two times a thickness of an individual lead of the plurality of flat leads. [0016] In one embodiment, the die paddle can be exposed on the second side of the semiconductor package and occupies at least two-thirds of an area of a surface of the second side. [0017] In one embodiment, the die paddle can dissipate heat generated from the semiconductor die, and the die paddle comprises copper. [0018] In one embodiment, at least one flat lead of the plurality of flat leads can include a wettable flank on an outward side outside of the molding compound. [0019] In one embodiment, the field effect transistor can switch a signal having a voltage in a range from 12 Volts to 150 Volts. [0020] Another aspect of the present disclosure is a semiconductor assembly that includes a semiconductor package and a printed circuit board. The semiconductor package includes a semiconductor die, a plurality of flat leads on a first side of the semiconductor package, and a heat spreader on a second side of the semiconductor package. The plurality of flat leads is electrically connected to the semiconductor die. The second side is positioned opposite the first side, and the heat spreader has a thickness that is at least 1.5 times a thickness of an individual lead of the plurality of leads. The semiconductor package is positioned on the printed circuit board so that the first side faces the printed circuit board. [0021] In one embodiment, at least one lead of the plurality of flat leads can include a wettable flank. Additionally, the wettable flank can be soldered on a corresponding contact point of the printed circuit board. [0022] In one embodiment, the heat spreader can include a groove. [0023] In one embodiment, the semiconductor die can include a field effect transistor. [0024] For purposes of summarizing the disclosure, certain aspects, advantages and novel features of the innovations have been described herein. It is to be understood that not necessarily all such advantages may be achieved in accordance with any particular embodiment. Thus, the innovations may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other advantages as may be taught or suggested herein. BRIEF DESCRIPTION OF THE DRAWINGS [0025] These and other features, aspects, and advantages of the disclosure are described with reference to the drawings of certain embodiments. It is to be understood that the accompanying drawings, which are incorporated in and constitute a part of this specification, are for the purpose of illustrating concepts disclosed herein and make not be to scale. [0026] FIGS. 1A, 1B, and 1C illustrate views of a semiconductor package according to some embodiments. [0027] FIGS. 2 and 3 illustrate top-down and bottom-down views of an embodiment of the semiconductor package of FIG.1A, respectively. [0028] FIG. 4 illustrates a cross-sectional view of an example semiconductor package through the line indicated by F-F in FIG.2. [0029] FIG. 5 illustrates a side view of an example semiconductor package according to embodiments. [0030] FIG. 6 illustrates a cross-sectional view of an example semiconductor package through the line E-E illustrated in FIG.5. [0031] FIG.7 illustrates a view of an example electrical contact according to some embodiments. [0032] FIG. 8 illustrates a view of an outer surface of an example die paddle according to some embodiments. [0033] FIG. 9 illustrates a view of an inner surface of a die paddle according to some embodiments. [0034] FIG. 10A illustrates an example of a lead frame according to some embodiments. [0035] FIGS. 10B and 10C illustrate example embodiments of a lead frame according to some embodiments. [0036] FIG. 11A illustrates an example of a one-piece die paddle with leads. [0037] FIG. 11B illustrates an example implementation of a semiconductor package according to some embodiments herein. [0038] FIG. 12A illustrates an example of a “gull wing” semiconductor package design. [0039] FIG. 12B illustrates an example embodiment of a packaging design with flat leads according to an embodiment that can have smaller inductive loop areas than the semiconductor package design of FIG.12A. [0040] FIG. 13A and 13B illustrate exploded views of an assembly for manufacturing semiconductor packages according to some embodiments. [0041] FIG. 14 illustrates an example embodiment of a sheet that comprises an array of support frames and lead frames. [0042] FIG. 15A shows a view of a semiconductor package before encapsulation according to some embodiments. [0043] FIG.15B shows a view of an assembled semiconductor package according to some embodiments. [0044] FIG. 16 illustrates an example assembly fixture used for manufacturing semiconductor packages. [0045] FIG.17 illustrates an exploded view of a semiconductor package according to some embodiments. [0046] FIGS. 18A and 18B illustrate side and bottom views, respectively, of a semiconductor package according to some embodiments. [0047] FIG.19A shows an example embodiment of a die paddle according to some embodiments. [0048] FIG. 19B shows an example embodiment of a die paddle that is partially encased in molding compound according to some embodiments. [0049] FIG. 20A illustrates an exploded view of a semiconductor package according to some embodiments. [0050] FIG. 20B illustrates a cross-section of an example embodiment of a semiconductor package. [0051] FIG.20C shows a view of an assembled semiconductor package according to some embodiments. [0052] FIG. 20D shows a view of an assembled semiconductor package according to some embodiments. [0053] FIG.21A shows a top view of a semiconductor package according to some embodiments. [0054] FIG.21B shows a bottom view of the semiconductor package of FIG.21A. [0055] FIG.21C shows an exploded view of an assembled semiconductor package in FIG.21A. DETAILED DESCRIPTION [0056] The following detailed description of certain embodiments presents various descriptions of specific embodiments. However, the innovations described herein can be embodied in a multitude of different ways, for example, as defined and covered by the claims. In this description, reference is made to the drawings where like reference numerals and/or terms can indicate identical or functionally similar elements. It will be understood that elements illustrated in the figures are not necessarily drawn to scale. Moreover, it will be understood that certain embodiments can include more elements than illustrated in a drawing and/or a subset of the elements illustrated in a drawing. Further, some embodiments can incorporate any suitable combination of features from two or more drawings. The headings provided herein are for convenience only and do not necessarily affect the scope or meaning of the claims. Introduction [0057] Electronic components containing one or more integrated circuit (IC) dies can be deployed in a wide variety of applications and in a wide variety of environmental conditions. For example, such components can form part of a power electronics system. In some cases, power electronics systems can be used to provide power for an electric vehicle. In some embodiments, power electronics systems can be part of a stationary energy storage system, such as a system for storing solar energy, a system for delivering power to a destination, and so forth. These are merely examples, and there are many other applications for such systems. In some cases, components can comprise diode switches, field effect transistors (FETs) such as metal-oxide-semiconductor FETS (MOSFETs) (e.g., GaN MOSFETs), insulated-gate bipolar transistors (IGBTs), other bipolar transistors, the like, or any suitable combination thereof. These components can generate significant heat during operation. [0058] Electronics systems, such as power electronic systems, can produce significant amounts of heat under both steady state load conditions and under surge conditions. Such heat can present significant problems. For example, excess heat can lead to reduced performance, reduced reliability, reduced lifespan, and so forth. For example, excessive thermal stresses can weaken solder joints, damage semiconductor components, or both. In some applications, surge loads can result in rapid temperature rises. High surge loads can be encountered in various applications such as, for example when starting portable compressors, HVAC systems, refrigeration systems, electric motors, power converters, or the like. The shape and height of conductive elements can also have a detrimental parasitic inductance effect with certain switching frequencies. Accordingly, there is a need for die packaging that can facilitate sufficient thermal transfer during steady state and surge load scenarios. Such die packaging can be designed with internal elements that are low in profile and close to a printed circuit board (PCB) when mounted. [0059] Certain conventional low-profile packaging designs have several drawbacks. For example, power dual flat no-lead (PDFN) packaging can have insufficient thermal mass to meet surge load heat absorption and/or transfer demands. Moreover, manufacturing certain PDFN semiconductor packages can be complex, costly, and time- consuming. For example, PDFN semiconductor packaging can involve the use of gull wings that can be formed by copper etching to achieve desired shapes. The use of PDFN semiconductor packaging typically involves limited thicknesses of copper (e.g., about 1.6 mm), block molding, grinding surfaces to expose a planar heat spreader, and the use of saw singulation to form discrete devices. As described herein, alternative approaches can lead to one or more of improved thermal performance, lower costs, lower complexity, or the like compared to conventional packaging. Package Design [0060] Aspects of this disclosure relate to semiconductor packages with relatively small inductance loop areas and relatively high surge load heat absorption. Such a semiconductor package can include a thick die paddle with area edges that reach close to an outer perimeter within manufacturable and reliability feasibility. This can provide a heat spreader with a relatively large area. Semiconductor package designs with a dedicated thick die paddle can provide a platform for steady-state heat transfer and transient thermal load capability to tether die temperatures within a manageable range for long-term reliability and performance. Since the die paddle is of relatively large thickness and shape, forming operations within a low-profile package manufacturing process can be limited. A thinner, more shape- formable lead frame can provide an electrical connection to a die backside as well as top surfaces of a semiconductor die. In embodiments disclosed herein, pre-formed lead frames can pre-position and arrange conductors in desirable shapes early in the assembly process. [0061] Aspects of the present disclosure can include a flat lead frame that enables a thinner profile (e.g., low profile) for the semiconductor package. For example, the flat lead frame disclosed herein can provide a thinner lead frame than lead frames with a gull wing structure. A flat lead can refer to a lead with a generally flat portion that extends outside of the molding material of a semiconductor package. Semiconductor packages disclosed herein can also include a die paddle that is significantly thicker than the flat lead frame. For example, the die paddle can be at least 1.5 times as thick as the flat lead frame. In some examples, the operational voltage range for the semiconductor components described herein can vary from 1 Volt (V) to 150 V, such as between 12 V and 150 V. In these examples, the flat lead frames can serve as electrical contact points (e.g., terminals) for the semiconductor package, where the flat lead frames have an appropriate thickness to facilitate the transfer of the generated current. For instance, the thickness of the flat lead frames can be a minimum of 5 mil or 0.127 mm. [0062] Embodiments disclosed herein can achieve similar thin, low-profile attributes as PDFN semiconductor packages while using high-volume and lower cost manufacturing processes. Such high-volume and lower cost manufacturing processes can include one or more of copper flattening, stamping, forging, discrete cavity encapsulation molding, or a punch cut singulation. Embodiments disclosed herein can be manufactured without surface grinding. [0063] In embodiments disclosed herein, heat transfer can be focused on a top side of a semiconductor package. Top side cooling can be desirable in certain applications due to bottom-side mounting surface temperature, PCB layout and/or feature considerations. The technology disclosed herein can be applied to dual-side cooled semiconductor packages. Certain designs can have conductor elements exposed on the top and bottom and can have design features to hold position during assembly and mold encapsulation. This can control molding flash and resin bleed. Accordingly, the need for grinding can be reduced or eliminated. In some examples, the die paddle (e.g., used for heat dissipation) can be exposed on the top surface of the packaged semiconductor. For example, 60% or more area of the top area of the semiconductor package can be the exposed surface of the die paddle. In certain instances, the die paddle can occupy at least two-thirds, 70%, or 80% of the area of a top surface of the semiconductor package. [0064] FIG. 1A illustrates a semiconductor package according to some embodiments. The semiconductor package 100 can include source contacts 102, drain contacts 104, and gate contacts 106. The source contacts 102, drain contacts 104, and gate contacts 106 can provide various electrical connections. For example, the source contacts 102, drain contacts 104, and gate contacts 106 can include source contacts, drain contacts, gate contacts, contacts for monitoring the semiconductor package 100 (e.g., contacts for temperature sensors such as a thermocouple), and so forth. In some embodiments, the source contacts 102, drain contacts 104, and gate contacts 106 can extend beyond the bulk of the semiconductor package 100. In some embodiments, the source contacts 102, drain contacts 104, and gate contacts 106 can be flush with an outer surface of the semiconductor package 100. In some embodiments, source contacts 102, drain contacts 104, and gate contacts 106 can be recessed in one or more directions from an outer surface of the semiconductor package 100. FIGS.1B and 1C illustrate an example design in which the source contacts 102 can unify to form a single piece rather than multiple individual leads, as shown in FIG.1A. [0065] While reference is made to source contacts, drain contacts, and gate contacts in the present disclosure, this is for illustrative purposes only. In general, stamped leads can be used to provide source terminals, gate terminals, drain terminals, Kelvin source terminals, control terminals, input terminals, output terminals, sensor terminals, base terminals, emitter terminals, collector terminals, ground terminals, reference terminals, shorting terminals, or any other suitable electrical terminal. [0066] The semiconductor packages shown in FIGS. 1A to 1C can include a top side heat spreader with a relatively large area. A top view 150A of the semiconductor package 100 is shown in FIG. 1B. FIG. 1B illustrates an example of a die paddle 200 and a molding compound 202 of the semiconductor package 100. The die paddle 200 can generally be referred to as a heat spreader of the semiconductor package 100. The die paddle 200 can function as a heat spreader in any suitable embodiments disclosed herein. The molding compound 202 can enclose components of the semiconductor package 100. In some cases, the die paddle 200 can provide a top side heat spreader with a relatively large area. For example, the top surface area 220 of the die paddle 200 (or the top exposed area of the die paddle 200) can be at least 60%, two thirds, 70%, or 80% of the top surface area 215 of the semiconductor package 100. The die paddle 200 can be composed of any suitable conductive material, such as copper or a copper alloy. [0067] FIG. 1B further illustrates an example of a bottom view 150B of the semiconductor package 100. As shown in FIG. 1B, the bottom view 150B can include the source contacts 102, drain contacts 104, and gate contacts 106. FIG. 1C further illustrates an internal view of 150C of the semiconductor package 100. Each of the source contacts 102, drain contacts 104, and gate contacts 106 can have a flat lead of the lead frame 600 that can extend outside of the semiconductor package 100. The lead frame 600 (e.g., flat lead) can include stamped leads. The thickness 252 of the lead frame 600 can be determined based on the operational voltage range for the semiconductor package 100 that can vary from 1 Volt (V) to 150 V, such as between 12 V and 150 V. In some examples, the thickness 252 of the lead frame 600 can be at least 5 mil or 0.127 mm. In some examples, each lead frame 600 can include a wettable flank 112 (e.g., wettable flank plate) on the outward facing side, for example, as illustrated in FIG.1B. [0068] FIG. 1C illustrates an exploded view of a semiconductor package 100 in accordance with some embodiments. As illustrated in FIG.1C, the semiconductor package 100 can include the lead frame 600. The lead frame 600 can include the source contacts 102, drain contacts 104, and gate contacts 106 (shown in FIG.1B). An integrated circuit (IC) die 400 can be positioned between the lead frame 600 and the die paddle 200. The IC die 400 can be referred to as a semiconductor die when the IC die 400 includes one or more semiconductor devices. In some examples, one or more field effect transistors (FETs) such as one or more metal-oxide-semiconductor field effect transistors (MOSFETs) (e.g., one or more GaN MOSFETs) can be implemented on the IC die 400. Thus, the IC die 400 can include terminals, such as the drain, source (and kelvin source), and gate terminals. In some embodiments, the die paddle 200 can have a thickness 210, sufficient to dissipate heat from transient events. The thickness 210 of the die paddle 200 can be at least 1.5 times thicker than the thickness 252 of an individual lead of the lead frame 600. In certain applications, the thickness 210 of the die paddle 200 can be at least 2 times, 2.5 times, or 3 times, a thickness 252 of an individual lead. The thickness 210 of a die paddle can be less than 10 times or less than 5 times the thickness 252 of an individual lead. The thicknesses 210 and 252 of the die paddle 210 and individual lead, respectively, are in a vertical dimension in the drawings. These thicknesses are in a direction orthogonal to the top and bottom surfaces of the semiconductor package. [0069] FIGS. 2 and 3 illustrate top-down and bottom-down views of the semiconductor package 100, respectively. FIG. 2 illustrates an example of top-down view of the semiconductor package 100. As illustrated in FIG.2, the top surface of the semiconductor package 100 can include a die paddle 200 portion (top exposed die paddle 200) surrounded by a molding compound 700. In some examples, the die paddle 200 portion can be composed of at least two-thirds of the top surface 310 of the semiconductor package 100. FIG. 2 also illustrates lead frames 600 (flat lead). [0070] FIG. 3 illustrates an example of bottom-down view of the semiconductor package 100. As illustrated in FIG. 3, the semiconductor package 100 can include the source contacts 102, drain contacts 104, and gate contacts 106, each contact having a flat lead frame shape. In some cases, the semiconductor package 100 can include exposed conductors 110A, 110B which may assist the assembly and molding processes. [0071] FIG.4 illustrates a cross-section of the semiconductor package 100 through the region indicated by F-F in FIG.2. As shown in FIG.4, the semiconductor package 100 can include a die paddle 200, die and lead attach structure 300 (e.g., solder, solder pre-form, conductive epoxy, sintering paste, and so forth), an IC die 400, source and gate attach structure 500 (e.g., solder, solder pre-form, solder bumping, conductive epoxy, sintering paste, and so forth), a lead frame 600, and molding compound 700. These components will be described in more detail herein. The IC die 400 can be a power IC or any other type of integrated circuit. In some embodiments, a discrete circuit, such as an operational amplifier constructed from individual transistors, can be implemented in place of the IC die 400. In some embodiments, the IC die 400 can include a combination of integrated and discrete components. In some embodiments, the package can be adapted for wire bonding. For example, the gate contact 106 can be shaped to accommodate wire bonding. In some embodiments, the lead frame 600 can be shaped to accommodate wire bonding. For example, a corner portion of the lead frame 600 can be removed to provide clearance for wire bonding or can be added to provide wire bonding surface area. [0072] In a typical flat no-lead package, the die paddle 200 occupies about the same area as the IC die 400. However, such an approach can limit the thermal performance of the die paddle 200. This limitation can present significant issues for power electronics. Such an issue can be especially pronounced under surge loads when large amounts of heat can be produced rapidly. Thus, in some embodiments, the die paddle 200 can extend substantially beyond the area of the IC die 400, for example, as illustrated in FIG. 4. As discussed in more detail below, features can be included in the die paddle 200 to impede or prevent the flow of die attach material (e.g., solder such as Sn-based solder, solder pre-form, conductive epoxy, sintering paste, and so forth) to areas substantially outside the area of the IC die 400. [0073] In some embodiments, heat extraction can be focused on one side of the semiconductor package 100. For example, the bottom surface (e.g., on the lead frame 600 side of the IC die 400) can be facing a carrier such as a printed circuit board, and thus may not be ideal for heat extraction due to the need to work around the constraints imposed by nearby components on the PCB, lead routing in the PCB, contact pads on the PCB, and so forth. [0074] As illustrated in FIG. 4, in some embodiments, the die paddle 200 can be thicker than the lead frame 600. This can help ensure that the IC die 400 is maintained in an acceptable temperature range during both steady-state operation and under surge loads. In some embodiments, the die paddle 200 and the IC die 400 can be about the same thickness. In some embodiments, the die paddle 200 can be thinner than the IC die 400. For example, in some embodiments, a PCB can include a thermally conductive insert, which may be referred to within the PCB industry as a “coin” (e.g., a copper coin) situated beneath the semiconductor package 100 when the semiconductor package 100 is mounted to the PCB. The coin can act as a thermal sink, enabling heat to be extracted effectively through the bottom of the semiconductor package 100. [0075] As further illustrated in FIG.4, the thickness 210 of the die paddle 200 can be at least 1.5 times, 2 times, 2.5 times, or 3 times thicker than the thickness 252 of the lead frame 600. Moreover, the area of the die paddle 200 (e.g., area corresponding to the length 200A and width of die paddle 200) can be at least 60%, two-thirds, 70%, or 80% of the top surface area (e.g., area corresponding to the length 410 and width of the semiconductor package shown in FIG. 4). [0076] FIG. 5 illustrates a side view of the semiconductor package 100 having stamped leads (flat lead) of a lead frame 600 (which can include, for example, one or more source contacts, one or more drain contacts, one or more gate contacts, and/or any other suitable electrical lead). The leads 600 are discussed in more detail below with reference to FIG.7. FIG.6 illustrates a cross-section of the semiconductor package 100 through the line E- E illustrated in FIG. 5. As shown in FIG. 6, the semiconductor package 100 includes a die paddle 200, die and lead attach structure 300, IC die 400, gate attached structure 500, lead frame 600, and molding compound 700. As illustrated in FIG.6, the lead frame 600 can be in electrical contact with the IC die 400 via the gate attach structure 500. The lead frame 600 can be configured such that source contacts 102, drain contacts 104, and gate contacts 106 are in contact with gate attach structure 500 and that the source contacts 102, drain contacts 104, and gate contacts 106 are not covered by the molding compound 700 and can be mounted to a carrier such as a printed circuit board. As described in more detail below, in some embodiments, the die and lead attach structure 300 and/or gate attach structure 500 can comprise solder, solder pre-form, conductive epoxy, sintering paste, etc. In some embodiments, the die and lead attach support frames 600 (see FIG.13A) and/or 650 (see FIG. 13A) can compress or deform during a molding process. [0077] As further illustrated in FIG.6, the thickness 210 of the die paddle 200 can be at least 1.5 times, 2 times, 2.5 times, or 3 times thicker than the thickness 252 of an individual lead of the lead frame 600. Moreover, the area of the die paddle 200 (e.g., the area corresponding to the length 200A and width of die paddle 200) can be at least 60%, two-thirds, 70%, or 80% of the top surface area (e.g., the area corresponding to the length 410 and width of the semiconductor package shown in FIG. 6). Furthermore, the semiconductor package of FIG. 6 can include flat lead frame 600 with flat leads that extend outside of the molding compound 700. The flat lead frame 600 can include stamped flat leads. [0078] FIG. 7 illustrates a view of a flat lead of the lead frame 600 according to some embodiments. In some embodiments, the flat lead can be stamped. As shown in FIG. 7, a flat lead can have a portion that is flush with the semiconductor package 100. In some embodiments, the flat lead can have a dimple 108. The dimple 108 can provide a cavity into which solder can flow during the attachment of the semiconductor package 100 to a carrier, such as a printed circuit board. In some embodiments, the dimple 108 can enable inspection of solder joints and/or the rework of solder joints. [0079] FIG. 8 illustrates a view of an outer surface of the die paddle 200 of the semiconductor package 100 according to some embodiments. In some embodiments, the outer surface can be exposed to the environment. In some embodiments, the outer surface can be embedded in a molding compound. The die paddle 200 can act as a heat spreader, and heat can be transported away from an IC die (e.g., IC die 400) to the outer surface of the die paddle 200. [0080] FIG.9 illustrates a view of an inner surface 204 of the die paddle 200 of the semiconductor package 100 according to some embodiments. As shown in FIG. 9, in some embodiments, the inner surface 204 can include a groove 206. The groove 206 can offer several advantages in certain applications. For example, groove 206 can act as a solder stop to limit or prevent the flow of solder into areas of the inner surface 204 where solder is not desired, or it can confine a volume of solder within an area to retain a desired solder thickness. In some embodiments, the groove 206 can operate as a mold lock to help keep the die paddle 200 in place with respect to other components during an assembly process. [0081] FIG. 10A illustrates an example of a lead frame 600 according to some embodiments. The lead frame 600 can include a lower portion 604 and an upper portion 606. The lower portion 604 can be in contact with the gate attach 500. The upper portion can be in contact with the die and lead attach 300. In some embodiments, the upper portion 606 can be in electrical communication with an IC die 400 via the die and lead attach 300 and the die paddle 200. As shown in FIG. 10A, the lead frame 600 can include various indentations that can serve as alignment features. The stepped features 602 can help ensure that components are secured by molding compound during the manufacturing process and the service life of the semiconductor package 100. [0082] Lead connections to the die paddle can straddle or fork or be placed alongside the die as well as hover over edges of the die. FIGS.10B and 10C illustrate example embodiments of a lead frame according to some embodiments. As shown in FIG. 10B, a lead frame can have die paddle connection forks 608. Such a configuration can allow the width W of the die paddle strip 610 to be kept relatively thin, which can maximize the area available to accommodate a larger die size. The paddle connection forks 608 can extend around the sides of an IC die, thereby increasing the copper (and/or other metal) mass adjacent to the die, which can improve thermal performance. In some embodiments, the metal of the lead frame 600 can extend over the IC die 400. In some embodiments, the forked structure of the die paddle can increase the stiffness of the die paddle. In some embodiments, the forked structure of the die paddle can improve mold locking such that components such as the die paddle, lead frame, and molding compound are less likely to shift relative to one another during temperature cycling during service. [0083] FIG. 10C illustrates another example embodiment of a lead frame. As shown in FIG.10C, additional thermal mass can be added by extending the paddle connection forks 608 along the edge of the die. In some embodiments, a conductive brim 612 can be included in a lead frame. In some embodiments, the conductive brim 612 can add additional thermal mass to the lead frame. In some embodiments, the conductive brim 612 can be exposed. In some embodiments, the conductive brim 612 can be embedded within mold compound. As illustrated in FIG. 10C, each flat lead can include a wettable flank 112 on the outward facing side of the flat lead frame 600. [0084] As mentioned above, a design according to the present disclosure can enable a larger die paddle 200 that can enable improved thermal transfer. FIG. 11A illustrates an example of a one-piece die paddle with leads. In such a design, there can be a lead frame 1102 and a die paddle 1104. As shown in FIG. 11A, the die paddle 1104 can have leads integrated into it. The size of the die paddle size is constrained because it does not extend over the leads. FIG. 11B illustrates an example implementation according to some embodiments herein. As shown in FIG. 11B, the die paddle 200 can be a separate component that does not have leads. The die paddle 200 can extend substantially over the lead frame 600. For example, the die paddle 200 can extend substantially over drain contacts 104. This can provide improved heat transfer surface area and thermal mass, which can aid in maintaining the IC die 400 at a suitable temperature under both steady state and surge load conditions. [0085] As discussed briefly above, inductance loops can pose significant problems for certain electronics. The conductors connected to the die can form loops whose proximity and spatial coupling can create undesirable electromagnetic effects. For example, parasitic inductance related to switching voltage, current, and/or frequency. Accordingly, it can be desirable to limit the area of any inductance loops. [0086] FIG. 12A illustrates an example of a “gull wing” design. As illustrated in FIG. 12A, an inductance loop 1202 formed by current flowing from source 1206 and drain 1208 can have a relatively large area. The “gull-wing” design can be a result of a manufacturing process that includes post-mold lead cutting and bending. [0087] Embodiments disclosed herein, such as FIG. 12B, can have a pre-shaped conductors with a low-profile and tight clearance for mold compound isolation and structural integrity. Such construction can result in reduced or minimized parasitic inductance loop length and area. The semiconductor package of FIG.12B has flat leads that are generally flat outside of the molding compound, unlike the leads in the gull wing design of FIG. 12A. [0088] FIG.12B illustrates an example embodiment of a packaging design that can have smaller inductive loop areas than the packaging design of FIG. 12A. As shown in FIG. 12B, an inductance loop 1204 can be formed as current flows from source contacts 102 to drain contacts 104. The length and area of the inductance loop 1204 can be substantially smaller than the length and area of the inductance loop 1202, reducing undesirable inductance effects. [0089] Conductors can be shaped to occupy inductance loop areas for purposes of reducing total loop area. Current path length may be similarly affected as desired. Proximity between conductors, capacitance, and spatial coupling can impact electromagnetic field effects. Operating parameters such as one or more of switching frequency, voltage, current rise rate, current fall rates, and conductive path electrical resistance can be tuned favorably by shapes of the conductors. Manufacturing and Assembly [0090] As discussed briefly above, certain semiconductor packaging can involve the use of processes that involve complex forming, etching, grinding, sawing, lead forming, and other processes. This can make fabricating semiconductor assemblies time-consuming, expensive, and prone to error. Advantageously, some structures and packaging described herein can be manufactured using simpler processes that overcome one or more of these limitations. [0091] Assembly of stacked subcomponents of individual variable thickness tolerance can utilize solder or paste bonding layers to absorb such tolerances to achieve a consistent overall stack height. Pre-shaped lead frames can have stepped height elements to conform elastically and inelastically during assembly and/or overmolding to allow the assembled stack to self gap-fill between lower and upper fixtures and mimic the closed height of mold tooling. Consistent overall height on opposing surfaces of an assembly stack can be desirable to minimize molding flash during overmolding, ideally limiting intrusion of molding compound onto conductor surfaces to be kept exposed such as leads and heat transfer surfaces. Pre-shaped (e.g., pre-stamped) lead frame structures with stepped heights may be fixtured during assembly for the die and lead bonding materials to absorb tolerance variations of stacked components. Pre-stamped conductors disclosed herein can be shaped to engage the die paddle and other components, such as IC dies, in a variety of ways and combinations. [0092] FIGS. 13A-B illustrate exploded views of an assembly according to some embodiments. FIG. 13B illustrates a flipped stacking/assembly orientation relative to FIG.13A. As shown in FIGS.13A-B, the assembly can include a die paddle 200, die and lead attach structure 300, IC die 400, gate attach structure 500, and lead frame 600. The die paddle 200 can be attached to a support frame 250. The lead frame 600 can be attached to a support frame 650. The support frames 250 and 650 can comprise, for example, a sheet of metal (e.g., copper). In some embodiments, the die paddle 200, the lead frame 600, or both can be stamped. For example, a sheet of material (e.g., a copper sheet or other metal sheet) can be stamped to form the die paddle 200 and support frame 250 or the lead frame 600 and support frame 650. The support frames can be used to facilitate easy assembly of a semiconductor package 100. The support frames can be removed (e.g., by stamping, sawing, etc.) to form a singulated semiconductor package 100. Using stamping to form the die paddle 200 and/or the lead frame 600 can enable the production of low-profile designs without a need for etching, thereby enabling faster and cheaper manufacturing. [0093] FIG. 14 illustrates an example embodiment of a sheet 1400 that comprises an array of support frames 650 and lead frames 600. Die paddles 200 and support frames 250 can similarly be prepared by stamping a sheet of a suitable metal (e.g., copper). [0094] FIG. 15A shows an unassembled view of a semiconductor package according to some embodiments. FIG. 15B shows a view of a completed semiconductor package according to some embodiments. In FIG.15B, the components are encased on one or more sides by molding compound 700. The components of the semiconductor package can have a feature and/or assembly height that is different from the final molded height. Moreover, due to tolerances in the manufacturing processes of the various components that make up the semiconductor package, there can be considerable variation in the feature height from package to package. Unequal feature, assembly, and mold heights can result in mold compound overflow. Conventional manufacturing approaches can include sacrificial material that can be polished or ground off after molding to ensure that molding material does not cover electrical contacts. This can add expense and complexity to manufacturing, as additional material is used which is later removed, and additional manufacturing steps are typically involved to ensure surface quality. [0095] According to some embodiments herein, lead frame and die paddle design can eliminate or substantially reduce the need for the use of sacrificial material and/or additional polishing or grinding steps. [0096] FIG.16 illustrates an example assembly fixture 1600. The assembly fixture 1600 can be made to have a mold height M, which can be the final height of the semiconductor package after molding. As discussed above, components (e.g., die paddle 200, IC die 400, and lead frame 600) can have varying heights that fit within manufacturing tolerances. In some embodiments, the die and lead attach structure 300 and/or gate attach structure 500 can comprise solder. In some embodiments, the die and lead attach structure 300 and/or gate attach structure 500 can comprise a compliant paste or other bonding material. In some embodiments, the compliant paste or bonding material may be flowable or liquid during assembly, fixturing, curing, and/or reflow processes. For example, the die and lead attach structure 300 and/or gate attach structure 500 can comprise a Sn-based solder, silver sintering paste, or an epoxy containing metallic particles. The compliant paste can allow the stack (e.g., die paddle 200, IC die 400, and lead frame 600 to “float” slightly (e.g., tens of micrometers) with respect to one another. As described above, the components of the semiconductor package can include, for example, support frame 250 and/or support frame 650. One or more components of the semiconductor package can include locking features that reduce or prevent excess movement of the components with respect to one another. When clamping the assembly fixture 1600, the compliant paste or other bonding material comprising the die and lead attach structure 300 and/or gate attach structure 500 can be compressed so that the overall height of the package matches the height of the mold. Such an approach can minimize mold flash that can appear on the outer surface of the lead frame 600 and/or the leads (e.g., source contacts 102, drain contacts 104, and/or gate contacts 106). In some embodiments, the die paddle 200 can elastically and/or inelastically deform to conform to the mold height. For example, a die paddle support frame (e.g., support frame 250) can be deflected during compression, for example by action of an assembly fixture. Additional Package Designs [0097] The package designs described above can have many advantages. However, the present disclosure is not limited to the above designs. Features, manufacturing processes, and so forth described herein can be incorporated into other semiconductor packages. [0098] FIG.17 illustrates an exploded view of a semiconductor package according to some embodiments. The semiconductor package 1700 can be broadly similar to the semiconductor package 100. The semiconductor package 1700 can be desirable for various components such as, for example, a bidirectional high electron mobility transistor (e.g., a bidirectional GaN HEMT). The semiconductor package can include a lead frame 1702. While the lead frame 1702 is broadly similar to the lead frame 600, there can be various differences. For example, the lead frame 1702 can have different heights such that contact can be made on either side of an IC die 1706. The semiconductor package lead frame elements can include additional conductors or contacts for other functions, for example connecting to die features for sensing such as contact 1707 and/or connection to the die paddle for electrically shorting such as contact 1708. [0099] FIGS. 18A and 18B illustrate side and bottom views of the semiconductor package 1700. As shown in FIG. 18A, the semiconductor package 1700 can include a top die connection 1812 and a die paddle connection 1814. As can be seen in FIGS. 18A, and 18B, the source contacts 1802 can contact both sides of the die 1706. For example, the source contacts 1802 (first source contacts) can contact the die 1706 and the contact 1708, and the contact 1708 can be in electrical contact with a side of the die 1706 opposite the side of the die 1706 that is in contact with the source contacts 1802 and the other source contacts 1804 (e.g., second source contacts). As shown in FIG.18B, various contacts can be included. For example, the semiconductor package 1700 can include a gate contact 1806A (e.g., first gate contact) and a Kelvin signal contact 1808A (first Kelvin signal contact). The semiconductor package 1700 can also include another gate contact 1806B (e.g., second gate contact), another Kelvin signal contact 1808B (second Kelvin signal contact), and a paddle contact 1810. In some examples, the paddle contact 1810 can prove internal connection to the source contact 1802 (first source contacts) or the another source contacts 1804 (second source contacts). In some embodiments, these contacts (1802, 1804, 1806A, 1806B, 1808A, 1808B, and 1810) can have the flat lead frame shape. [0100] FIG.19A shows an example embodiment of a die paddle 1900 according to some embodiments. As shown in FIG. 19A, in some embodiments, the die paddle 1900 can have contacts 1902 built in rather than being electrically connected to contacts that are a discrete component. In some embodiments, the die paddle 1900 can include features such as the pads 1904 that can help to ensure that the die paddle 1900 is positioned correctly. In some embodiments, the pads 1904 can elastically or inelastically compress at various stages of assembly or molding. [0101] FIG.19B shows an example of a die paddle (e.g., the die paddle 1900) after molding according to some embodiments. As shown in FIG. 19B, the die paddle 1900 can be partially encased in molding 1910. In some embodiments, the contacts 1902 can have wettable flanks 1908. The wettable flanks 1908 can aide in mounting (e.g., soldering) an IC package to a circuit board. [0102] FIGS. 20A-D illustrate an example of a package according to some embodiments. FIG. 20A illustrates an exploded view of a package according to some embodiments. In FIG. 20A, a package can include a die paddle 2000, die and lead attach structure 3000 (e.g., solder, solder pre-form, conductive epoxy, sintering paste, and so forth), IC die 4000, gate attach structure 5000 (e.g., solder, solder pre-form, conductive epoxy, sintering paste, and so forth), and lead frame 6000. The lead frame 6000 can be attached to a support frame 6050, for example to facilitate manufacturing. In some embodiments, the lead frame can have coplanar areas 6010, for example where the lead frame 6000 contacts the IC die 4000 via the gate attach structure 5000. The coplanar areas 6010 can be a coplanar stencil print. As shown in FIG.20A, a top surface of the die paddle 2000 may not be at a single height. For example, the top surface of the die paddle 2000 can have a stepped structure. The die paddle 2000 can be a clip heat spreader. [0103] FIG.20B illustrates a side view of the semiconductor package illustrated in FIG.20A. As shown in FIG.20B, a cutaway region 2050 can be removed (or not formed) from the die paddle 2000, thereby providing a multi-gage structure. This cutaway region 2050 can enable the use of a large die paddle 2000 that extends closer to the edges of a package while maintaining structural integrity. Such a configuration can provide an increased surface area of the die paddle 2000, which can enable better thermal performance. As shown in FIG. 20C, a completed package can encase the die paddle 2000, die and lead attach structure 3000, IC die 4000, gate attach structure 5000, and lead frame 6000 in molding compound 7000. The molding compound 7000 can extend at least partially over the die paddle 2000. For example, the molding compound 7000 can occupy the cutaway region 2050. [0104] As further illustrated in FIG.20C, the thickness 210 of the die paddle 2000 can be at least 1.5 times thicker than the thickness 252 of the lead frame 6000. Moreover, the area of the die paddle 2000 (e.g., area corresponding to the length 200A of die paddle 2000) can be at least 60 % of the top surface area (e.g., area corresponding to the length 410 of the semiconductor package shown in FIG.20B). Furthermore, the semiconductor package of FIG. 20B can include flat lead of the lead frame 600 that extends outside of the molding compound 7000. [0105] FIG.20D illustrates a completed package according to some embodiments. As shown in FIG. 20D, the die paddle 2000 can be partially exposed and partially covered by molding compound 7000. The package can include contacts 2002. In some embodiments, the contacts 2002 can include wettable flanks 2008, for example, as described above with respect to FIG.19B. [0106] FIGS.21A-21C illustrates an example of semiconductor package 2100 that can implement the die paddle and flat lead frame in accordance with some embodiments. The semiconductor package 2100 is an example of a semiconductor package where the leads are included on shorter sides of the semiconductor package. In other embodiments discussed above, leads are included on longer sides of semiconductor packages. Leads can be positioned on any suitable side or sides of a semiconductor package in accordance with any suitable principles and advantages disclosed herein. FIG. 21A illustrates a top side view of the semiconductor package 2100. The semiconductor package 2100 can include a molding compound 2110 that can enclose components of the semiconductor package 2100. The molding compound 2110 can be made of a rigid mold resin. [0107] FIG.21B illustrates a bottom view of the semiconductor package 2100. The semiconductor package 2100 can include drain contact(s) 2122, source contact(s) 2132, gate terminal 2142, and Kelvin source terminal 2134. [0108] FIG. 21C illustrates an exploded view of the semiconductor package 2100 according to some embodiments. The semiconductor package 2100 can be mounted on a frame 2352 and assembled with other the semiconductor packages. In some embodiments, the frame 2352 can provide mechanical support and the electrical contact in the assembly. [0109] As shown in FIG.21C, the semiconductor package 2100 can include a layer of bonding material 2312, a die 2314, a layer of die attach material 2316, and a mold resin packaging structure 2310, and a die paddle 2320 (e.g., die clip). In some examples, the layer of bonding material 2312 can be formed based on a pattern that can include multiple areas to provide electrical bonding with corresponding die connection terminals (e.g., contact terminals), such as source (including Kelvin source), drain, and gate of a semiconductor component. For example, the die attach pads 2312A, 2312B, 2312C, and 2312D can provide electrical connections to the drain terminal, the source terminal, the gate terminal, and the Kelvin source terminal of the die connection terminals, respectively. In some examples, the layer of die attach material 2312 can be formed by a conductive material, such as solder, conductive epoxy, and the like. Additional Embodiments [0110] In the foregoing specification, the disclosure has been described with reference to specific embodiments. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the disclosure. The specification and drawings are, accordingly, to be regarded in an illustrative rather than restrictive sense. [0111] Indeed, although this disclosure is in the context of certain embodiments and examples, it will be understood by those skilled in the art that the inventions extend beyond the specifically disclosed embodiments to other alternative embodiments and/or uses of the inventions and equivalents thereof. In addition, while several variations of the embodiments have been shown and described in detail, other modifications, which are within the scope of this disclosure, will be readily apparent to those of skill in the art based upon this disclosure. It is also contemplated that various combinations or sub-combinations of the specific features and aspects of the embodiments may be made and still fall within the scope of the disclosure. It should be understood that various features and aspects of the disclosed embodiments can be combined with, or substituted for, one another in order to form varying modes of the embodiments disclosed herein. Any methods disclosed herein need not be performed in the order recited. Thus, it is intended that the scope of the disclosure should not be limited by the particular embodiments described above. [0112] It will be appreciated that the systems and methods of the disclosure each have several innovative aspects, no single one of which is solely responsible or required for the desirable attributes disclosed herein. The various features and processes described above may be used independently of one another or may be combined in various ways. All possible combinations and sub-combinations are intended to fall within the scope of this disclosure. [0113] Certain features that are described in this specification in the context of separate embodiments also may be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment also may be implemented in multiple embodiments separately or in any suitable sub-combination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination may in some cases be excised from the combination, and the claimed combination may be directed to a sub- combination or variation of a sub-combination. No single feature or group of features is necessary or indispensable to each and every embodiment. [0114] It will also be appreciated that conditional language used herein, such as, among others, “can,” “could,” “might,” “may,” “e.g.,” and the like, unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements and/or steps. Thus, such conditional language is not generally intended to imply that features, elements and/or steps are in any way required for one or more embodiments or that one or more embodiments necessarily include logic for deciding, with or without author input or prompting, whether these features, elements and/or steps are included or are to be performed in any particular embodiment. The terms “comprising,” “including,” “having,” and the like are synonymous and are used inclusively, in an open- ended fashion, and do not exclude additional elements, features, acts, operations, and so forth. In addition, the term “or” is used in its inclusive sense (and not in its exclusive sense) so that when used, for example, to connect a list of elements, the term “or” means one, some, or all of the elements in the list. In addition, the articles “a,” “an,” and “the” as used in this application and the appended claims are to be construed to mean “one or more” or “at least one” unless specified otherwise. Similarly, while operations may be depicted in the drawings in a particular order, it is to be recognized that such operations need not be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Further, the drawings may schematically depict one or more example processes in the form of a flowchart. However, other operations that are not depicted may be incorporated in the example methods and processes that are schematically illustrated. For example, one or more additional operations may be performed before, after, simultaneously, or between any of the illustrated operations. Additionally, the operations may be rearranged or reordered in other embodiments. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems may generally be integrated together in a single software product or packaged into multiple software products. Additionally, other embodiments are within the scope of the following claims. In some cases, the actions recited in the claims may be performed in a different order and still achieve desirable results. [0115] Further, while the methods and devices described herein may be susceptible to various modifications and alternative forms, specific examples thereof have been shown in the drawings and are herein described in detail. It should be understood, however, that the disclosure is not to be limited to the particular forms or methods disclosed, but, to the contrary, the disclosure is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the various implementations described and the appended claims. Further, the disclosure herein of any particular feature, aspect, method, property, characteristic, quality, attribute, element, or the like in connection with an implementation or embodiment can be used in all other implementations or embodiments set forth herein. Any methods disclosed herein need not be performed in the order recited. The methods disclosed herein may include certain actions taken by a practitioner; however, the methods can also include any third-party instruction of those actions, either expressly or by implication. The ranges disclosed herein also encompass any and all overlap, sub-ranges, and combinations thereof. Language such as “up to,” “at least,” “greater than,” “less than,” “between,” and the like includes the number recited. Numbers preceded by a term such as “about” or “approximately” include the recited numbers and should be interpreted based on the circumstances (e.g., as accurate as reasonably possible under the circumstances, for example ±5%, ±10%, ±15%, etc.). Phrases preceded by a term such as “substantially” include the recited phrase and should be interpreted based on the circumstances (e.g., as much as reasonably possible under the circumstances). For example, “substantially constant” includes “constant.” Unless stated otherwise, all measurements are at standard conditions including temperature and pressure. [0116] As used herein, a phrase referring to “at least one of” a list of items refers to any combination of those items, including single members. As an example, “at least one of: A, B, or C” is intended to cover: A, B, C, A and B, A and C, B and C, and A, B, and C. Conjunctive language such as the phrase “at least one of X, Y and Z,” unless specifically stated otherwise, is otherwise understood with the context as used in general to convey that an item, term, etc. may be at least one of X, Y or Z. Thus, such conjunctive language is not generally intended to imply that certain embodiments require at least one of X, at least one of Y, and at least one of Z to each be present. The headings provided herein, if any, are for convenience only and do not necessarily affect the scope or meaning of the devices and methods disclosed herein. [0117] Accordingly, the claims are not intended to be limited to the embodiments shown herein but are to be accorded the widest scope consistent with this disclosure, the principles and the novel features disclosed herein.

Claims

WHAT IS CLAIMED IS: 1. A semiconductor package comprising: a semiconductor die; a plurality of flat leads on a first side of the semiconductor package, the plurality of flat leads being electrically connected to the semiconductor die; and a heat spreader on a second side of the semiconductor package, the second side being opposite the first side, and the heat spreader having a thickness that is at least 1.5 times a thickness of an individual lead of the plurality of flat leads.

2. The semiconductor package of Claim 1, wherein the heat spreader occupies more than two-thirds of an area of a surface of the second side.

3. The semiconductor package of Claim 1, wherein the heat spreader occupies more than 70% of an area of a surface of the second side.

4. The semiconductor package of Claim 1, wherein the thickness of the heat spreader is at least 2 times the thickness of the individual lead.

5. The semiconductor package of Claim 1, wherein the thickness of the heat spreader is less than 10 times the thickness of the individual lead.

6. The semiconductor package of Claim 1, wherein the heat spreader comprises copper.

7. The semiconductor package of Claim 1, wherein at least one lead of the plurality of flat leads comprises a wettable flank.

8. The semiconductor package of Claim 1, wherein the semiconductor die comprises a switch.

9. The semiconductor package of Claim 1, wherein: the semiconductor die comprises a field effect transistor having a gate, a source, and a drain, and the plurality of flat leads comprise a gate lead connected to the gate, a source lead connected to the source, and a drain lead connected to the drain.

10. The semiconductor package of Claim 1, further comprising a molding compound enclosing the semiconductor die, wherein each lead of the plurality of flat leads extends beyond the molding compound such that the exposed portion of the lead is flat.

11. A semiconductor package comprising: a molding compound; a semiconductor die comprising a field effect transistor having a source, a gate, and a drain, the semiconductor die being enclosed by the molding compound; a plurality of flat leads on a first side of the semiconductor package, the plurality of flat leads comprising a source lead connected to the source, a gate lead connected to the gate, and a drain lead connected to the drain, and each flat lead extends outside of the molding compound; and a die paddle on a second side of the semiconductor package, the second side being opposite the first side, and the die paddle having a thickness that is at least 2 times a thickness of an individual lead of the plurality of flat leads.

12. The semiconductor package of Claim 11, wherein the die paddle is exposed on the second side of the semiconductor package and occupies at least two-thirds of an area of a surface of the second side.

13. The semiconductor package of Claim 11, wherein the die paddle is configured to dissipate heat generated from the semiconductor die, and the die paddle comprises copper.

14. The semiconductor package of Claim 11, wherein at least one flat lead of the plurality of flat leads comprises a wettable flank on an outward side outside of the molding compound.

15. The semiconductor package of Claim 11, wherein the field effect transistor is configured to switch a signal having a voltage in a range from 12 Volts to 150 Volts.

16. A semiconductor assembly comprising: a semiconductor package comprising: a semiconductor die; a plurality of flat leads on a first side of the semiconductor package, the plurality of flat leads being electrically connected to the semiconductor die; and a heat spreader on a second side of the semiconductor package, the second side being opposite the first side, and the heat spreader having a thickness that is at least 1.5 times a thickness of an individual lead of the plurality of leads; and a printed circuit board, the semiconductor package positioned on the printed circuit board such that the first side is facing the printed circuit board.

17. The semiconductor assembly of Claim 16, wherein at least one lead of the plurality of flat leads comprises a wettable flank, and wherein the wettable flank is soldered on a corresponding contact point of the printed circuit board.

18. The semiconductor assembly of Claim 16, wherein the heat spreader comprises a groove.

19. The semiconductor assembly of Claim 16, wherein the semiconductor die comprises a field effect transistor.