EP4637268A1

EP4637268A1 - Dimmable driving circuit

Info

Publication number: EP4637268A1
Application number: EP23902773.3A
Authority: EP
Inventors: Lei Zhao
Original assignee: Opple Lighting Co Ltd; Suzhou Op Lighting Co Ltd
Current assignee: Opple Lighting Co Ltd; Suzhou Op Lighting Co Ltd
Priority date: 2022-12-16
Filing date: 2023-12-13
Publication date: 2025-10-22
Also published as: WO2024125579A1

Abstract

The present application discloses a dimmable driving circuit, comprising: a preceding-stage converter, which is coupled with an external power supply and outputs a first voltage; a dimming driving module, which is coupled with both the preceding-stage converter and an external load, receives the first voltage, outputs a second voltage, and drives the external load to work; a first detection circuit, which is coupled with the preceding-stage coupler, receives the first voltage, and outputs a first detection signal representing the first voltage; a second detection circuit, which is coupled with the dimming driving module, receives the second voltage, and outputs a second detection signal representing the second voltage; and a main control module, which receives the first detection signal and the second detection signal, outputs an adjustment signal, and sends the adjustment signal to the preceding-stage converter, wherein the preceding-stage converter adjusts the value of the first voltage, the ratio of the second voltage to the first voltage being maintained at a preset value. The dimmable driving circuit of the present application can reduce pause in a dimming process.

Description

This present application claims priority to Chinese Patent Application No. 202211627429.4, filed one December 16, 2022 , and entitled "Dimmable Driving Circuit", and Chinese Patent Application No. 202223397258.9, filed on December 16, 2022 , and entitled "Dimmable Driving Circuit", the entire contents of which are incorporated herein by reference.

TECHNICAL FIELD

The present application relates to the technical field of integrated circuit design, and in particular to a dimmable driving circuit.

BACKGROUND

The development of smart lighting has risen rapidly in recent two years, and during this period, the dimming function has been particularly sought after. Now, an excellent smart lighting will require its dimming driving circuit to have a silky dimming effect, so that the overall visual effect will be more comfortable and more consistent with the human eye's requirements for optics; that is, the dimming effect is required not to jitter during any of the brightness and dimming processes, because the jitter of the light gives a dangerous feeling to people. PWM chopper dimming is a dimming driving scheme with very high performance-price ratio, which can achieve a dimming depth of one thousandth or even one thousandth, and meet all kinds of dimming requirements.

TECHNICAL PROBLEM

However, in response to that two PWM dimming signals change exactly in the discharge period of the inductor, the current in the inductor will not actually increase and the brightness of the lamp will not change. Please refer to Fig. 1, in the following figure, an effective high level of the previous PWM dimming signal continues to a position a, and an effective high level of the latter PWM dimming signal continues to a position b, that is, the length of the effective high level of the two front and rear PWM dimming signals changes from the position a to the position b, and the length of the effective high level increases. Theoretically, the brightness of the lamp will change a little brighter; however, because the changes in these two PWM dimming signals fall exactly in the discharge period of the inductor, as shown by the dashed period in the above figure (the working frequency of the inductor is otherwise determined), the current in the inductor (and also the current flowing through the bead) does not actually increase, so the brightness of the bead does not change. In this way, it is necessary to wait until the effective high level of the subsequent PWM dimming signal falls within the charge period of the inductor. At this time, the current of the inductor directly works according to the current corresponding to the subsequent PWM dimming signal, that is, the current directly jumps and increases, and the brightness of the lamp bead also directly jumps and becomes brighter, which is the pause (jitter) in dimming; the pause is more pronounced in response to changes in successive PWM dimming signals fall within the discharge period of the inductor.
In this regard, a direct corresponding solution is to detect and determine the effective high level time of the PWM dimming signal and the charge period and discharge period of the inductor, so that the effective high level time of the PWM dimming signal falls within the charge period of the inductor as much as possible, but obviously, the specific implementation of this solution is unusually difficult.

TECHNICAL SOLUTIONS

Embodiments of the present application provide a dimmable driving circuit to solve the problem of pause in the dimming process.
An embodiment of the present application provides a dimmable driving circuit, including:

a preceding-stage converter, coupled with an external power supply and configured to output a first voltage;
a dimming driving module, coupled with both the preceding-stage converter and an external load, and configured to receive the first voltage, outputting a second voltage, and drive the external load to work;
a first detection circuit, coupled with the preceding-stage converter, configured to receive the first voltage and output a first detection signal representing the first voltage;
a second detection circuit, coupled with the dimming driving module, configured to receive the second voltage and output a second detection signal representing the second voltage;
a main control module, coupled with the first detection circuit, the second detection circuit and the preceding-stage converter, and configured to receive the first detection signal and the second detection signal, output an adjustment signal, and send the adjustment signal to the preceding-stage converter, the preceding-stage converter adjusts a value of the first voltage, a ratio of the second voltage to the first voltage is maintained at a preset value.

In some embodiments, the dimmable driving circuit further includes a voltage reference and feedback loop, the voltage reference and feedback loop is coupled with both the main control module and the preceding-stage converter, is configured to receive the adjustment signal output by the main control module, generate a feedback signal and sent the feedback signal to the preceding-stage converter, the preceding-stage converter adjusts the value of the first voltage according to the feedback signal.
In some embodiments, the main control module includes a main control chip, the main control chip includes a first pin as a power supply pin coupled with an working power supply; the main control chip includes a second pin as a first detection pin coupled with the first detection circuit and configured to receive the first detection signal output by the first detection circuit; the main control chip includes a third pin as a second detection pin coupled with the second detection circuit and configured to receive the second detection signal output by the second detection circuit; the main control chip includes a third pin as an adjustment signal output pin, configured to output the adjustment signal; the main control chip includes an eighth pin as a ground pin coupled with a signal ground.
In some embodiments, the main control chip includes a seventh pin as a dimming signal output pin, coupled with the dimming driving module, and configured to output a dimming signal to the dimming driving module.
In some embodiments, the first pin of the main control chip is coupled with the preceding-stage converter via a voltage conversion chip.
In some embodiments, the dimming driving module includes a dimming chip including a second pin as a dimming signal input pin, and coupled with the signal ground via a second resistor; the dimming chip includes a third pin as a power supply pin coupled with the signal ground via a first capacitor, coupled with the preceding-stage converter via a first resistor, and configured to receive the first voltage; the dimming chip includes a fifth pin as a driving pin coupled with the external load via a second inductor, and coupled with the preceding-stage converter via a first diode, an anode electrode of the first diode is coupled with the first voltage, a cathode electrode of the first diode is coupled with the fifth pin of the dimming chip; the dimming chip includes a seventh pin as a ground pin, coupled with the signal ground.
In some embodiments, the dimming driving module is a PWM chopper dimming driving circuit, and the dimming signal is a PWM signal.
In some embodiments, the first detection circuit includes a ninth resistor and an eleventh resistor connected in series, a free end of the ninth resistor is coupled with the preceding-stage converter and configured to receive the first voltage, a free end of the eleventh resistor is coupled with a signal ground, a coupling point of the ninth resistor and the eleventh resistor is configured to output the first detection signal; the second detection circuit includes a fourth resistor and a tenth resistor connected in series, a free end of the fourth resistor is coupled with the dimming driving module and configured to receive the second voltage, a free end of the tenth resistor is coupled with the signal ground, a coupling point of the fourth resistor and the tenth resistor is configured to output the second detection signal.
In some embodiments, the voltage reference and feedback loop includes a reference voltage chip and an optocoupler, the reference voltage chip includes a third pin as a ground pin, which is coupled with a signal ground; the reference voltage chip includes a second pin as a power supply pin, which is coupled with the preceding-stage converter via a sixteenth resistor and a seventeenth resistor connected in series, and receives the first voltage; the reference voltage chip includes a first pin as an adjustment pin, coupled with the main control module via a twenty-third resistor, and configured to receive the adjustment signal, the first pin of the reference voltage chip is further coupled with the signal ground via a twentieth resistor, further coupled with the pre-converter via an eighteenth resistor, and further coupled with a second pin of the reference voltage chip via an eighth capacitor and a twenty-first resistor connected in series; the optocoupler includes a first pin and a second pin, connected in parallel with both ends of the seventeenth resistor, the optocoupler includes a third pin coupled with a power ground, the optocoupler includes a fourth pin coupled with the preceding-stage converter, and configured to output the feedback signal, and sends the feedback signal to the preceding-stage converter.
In some embodiments, the preceding-stage converter includes an auxiliary control chip, a power transistor and a transformer, the auxiliary control chip includes an eighth pin as a feedback pin coupled with the voltage reference and the feedback loop, configured to receive a feedback signal provided by the voltage reference and feedback loop, the eighth pin of the auxiliary control chip is further coupled with the power ground via a third capacitor; the auxiliary control chip includes a second pin as a power supply pin, coupled with the transformer via a sixth resistor and a third diode connected in series, and is further coupled with the power ground via a third electrolytic capacitor; the auxiliary control chip includes a seventh pin as a ground pin, coupled with the power ground; the auxiliary control chip includes a fifth pin as a control pin, coupled with the transformer via the power transistor.
In some embodiments, the preceding-stage converter further includes a rectifier bridge, an input end of the rectifier bridge is coupled with the external power supply, and a first electrolytic capacitor is connected in parallel between two of output ends of the rectifier bridge, and one of the two of output ends of the rectifier bridge is then coupled with the transformer.
In some embodiments, the transformer includes a first pin and a third pin, and the first pin and the third pin of the transformer is provided with a primary winding of the transformer therebetween, the first pin of the transformer is coupled with a first end of an output end of the rectifier bridge, a second end of the output end of the rectifier bridge is coupled with a power ground, and the third pin of the transformer is coupled with a drain electrode of the power transistor.
In some embodiments, the transformer further includes a fifth pin and a sixth pin, and the fifth pin and the sixth pin of the transformer is provided with an auxiliary winding of the transformer therebetween, the fifth pin of the transformer is coupled with a power ground, and the sixth pin of the transformer is coupled with the second pin of the auxiliary control chip via the third diode and the sixth resistor connected in series.
In some embodiments, the transformer further includes a ninth pin and a tenth pin, the ninth pin and the tenth pin of the transformer is provided with a secondary winding of the transformer therebetween, a fourth diode and a fourth electrolytic capacitor are connected in series between the ninth pin and the tenth pin of the transformer, and the tenth pin of the transformer is coupled with the signal ground, and a coupling point of the fourth diode and the fourth electrolytic capacitor outputs the first voltage.
In some embodiments, the auxiliary control chip further includes a sixth pin as a sampling pin, coupled with the power ground via a fourth capacitor, coupled with the power ground via a twelfth resistor, and coupled with a source electrode of the power transistor.

BENEFICIAL EFFECTS

The dimmable driving circuit of the embodiment of the present application obtains the first voltage output by the preceding-stage converter (that is, the input voltage of the dimming driving module) and the second voltage output by the dimming driving module (that is, the input voltage of the dimming driving module, or the load voltage). According to different load voltages (such as different external loads, that is, the second voltage) and the preset value of the ratio of the second voltage to the first voltage (the highest value of the duty ratio of the dimming driving module), the value of the first voltage output by the preceding-stage converter is adjusted so that the ratio of the second voltage to the first voltage is maintained at the preset value, thereby reducing the discharge period of the inductor in the dimming driving module, and also minimizing the chance that the change of the dimming signal falls within the discharge period of the inductor, thereby reducing the pause in the dimming process and improving the user experience.

BRIEF DESCRIPTION OF DRAWINGS

The drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the embodiments of the present application. For those skilled in the art, under the premise of not paying creative efforts, other drawings can also be obtained based on these drawings.

Fig. 1 is a schematic diagram of a waveform of a current of an inductor and a dimming signal in a common dimmable driving circuit;
Fig. 2 is a schematic diagram of a waveform of a current of an inductor in a dimmable driving circuit provided by an embodiment of the present application;
Fig. 3 is a schematic structural diagram of a dimmable driving circuit provided by an embodiment of the present application.

DETAILED DESCRIPTION

The technical solutions in the embodiments of the present application will be clearly and completely described below. Obviously, the described embodiments are only some of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of protection of the present application.
The technical solution of the present application provides a dimmable driving circuit, which is described in detail below. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments of the present application. And in the following embodiments, the description of each embodiment has its own emphasis. For portions that are not detailed in a certain embodiment, please refer to the relevant descriptions of other embodiments.
The present application proposes that, in response to that the duty ratio of the PWM chopper dimming circuit is increased as much as possible, for example, 100% in the extreme ideal state, that is, the ratio of the output voltage to the input voltage of the PWM chopper dimming circuit is increased, the discharge period of the inductor can be minimized, please refer to the dotted line period in Fig. 2, in this way, it is easier to avoid changes in the PWM dimming signal from falling within the discharge period of the inductor, thereby reducing the pause in dimming.
Referring to Fig. 3, a first embodiment of the present application provides a dimmable driving circuit, including:

a preceding-stage converter 10, which is coupled with an external power supply and outputs a first voltage V1;
a dimming driving module 20, which is coupled with both the preceding-stage converter 10 and the external load 70, receives the first voltage V1, outputs a second voltage V2, and drives the external load 70 to work;
a first detection circuit 30, which is coupled with the preceding-stage converter 10, receives the first voltage V1, and outputs a first detection signal ADC_V1 representing the first voltage V1;
a second detection circuit 40, which is coupled with the dimming driving module 20, receives the second voltage V2, and outputs a second detection signal ADC_V2 representing the second voltage V2;
a main control module 50, which is coupled with the first detection circuit 30, the second detection circuit 40, and the preceding-stage converter 10, receives the first detection signal ADC_V1 and the second detection signal ADC_V2, outputs an adjustment signal DAC_ADJ, and sends the adjustment signal DAC_ADJ to the preceding-stage converter 10, in which the preceding-stage converter 10 adjusts the value of the first voltage V1, and the ratio of the second voltage V2 to the first voltage V1 is maintained at a preset value.

The first voltage V1 is provided to the dimming driving module 20, which may also be referred to as an input voltage of the dimming driving module 20. The second voltage V2 is output from the dimming driving module 20, which may also be referred to as an output voltage of the dimming driving module 20, and is applied to the external load 70, which may also be referred to as a load voltage. In some embodiments, the external load 70 is an LED bead, and multiple or multiple groups of LED beads may be connected in series and/or in parallel; the second voltage V2 is applied to the cathode electrode of the LED bead, and the anode electrode of the LED bead is coupled with the first voltage V1. The ratio of the second voltage V2 to the first voltage V1 may also be referred to as a duty ratio D of the dimming driving module 20. In general, the maximum value of the duty ratio D of a dimming driving module 20 can be clarified during design according to various parameter requirements of the dimming driving module 20 and subsequent test verification, and the clarified maximum value of the duty ratio D is stored in the dimming driving module 20 as a preset value. For example, in a specific embodiment, the maximum value of the duty ratio D may be 94%, or 95%. In general, the duty ratio D is preferably greater than 80%, in particular greater than 90%. The present application adjusts the first voltage V1 (the input voltage of the dimming driving module 20) by detecting the load voltage (the second voltage V2, which is different in response to be coupled with different external loads 70), so that the ratio of the second voltage V2 to the first voltage V1 is maintained at a preset value, that is, a higher duty ratio D, such as 94% or 95%. In this way, no matter what kind of external load 70 is coupled with the dimming driving circuit of the present application, the discharge period of the inductor in the dimming driving module 20 will be as small as possible, so as to avoid the change of the dimming signal falling within the discharge period of the inductor, thereby reducing the pause in dimming and giving the user a better user experience.
In some embodiments, the main control module 50 includes a main control chip U5, and the main control chip U5 has a first pin as a power pin which is coupled with a working power supply; the main control chip U5 has a second pin as the first detection pin CS/PA7, which is coupled with the first detection circuit 30 and receives the first detection signal ADC_V1 output by the first detection circuit 30; the main control chip U5 has a third pin as the second detection pin TKS/PA6, which is coupled with the second detection circuit 40 and receives the second detection signal ADC_V2 output by the second detection circuit 40; the main control chip U5 has a third pin as an adjustment signal output pin RSTB/PA5, which outputs the adjustment signal DAC_ADJ; the main control chip U5 has an eighth pin as a ground pin, which is coupled with a signal ground SGND. As before, the main control module 50 stores the preset value of the ratio of the second voltage V2 to the first voltage V1, that is, the highest value of the duty ratio D of the dimming driving module 20; in addition, the first detection signal ADC_V1 obtained actually represents the actual value of the first voltage V1, and the second detection signal ADC_V2 obtained actually represents the actual value of the second voltage V2, in this way, after judgment, comparison and calculation, an adjustment signal DAC_ADJ can be output, which is used to represent the ideal value that the first voltage V1 can reach. For example, in a specific embodiment, a current actual value of the first voltage V1 is 24V, but by comparing and calculating the second voltage V2 and the highest value (preset value) of the duty ratio D, it is get that the ideal value of the first voltage V1 should be better to be 22V, so the adjustment signal DAC_ADJ output represents this 22V.
In some embodiments, the adjustment signal DAC_ADJ is an analog signal. This analog signal cannot directly control the preceding-stage converter 10 to change the output first voltage V1. Therefore, in some embodiments, the dimmable driving circuit further includes a voltage reference and feedback loop 60, which is coupled with both the main control module 50 and the preceding-stage converter 10, receives the adjustment signal DAC_ADJ output by the main control module 50, generates a feedback signal FB, and sends the feedback signal FB to the preceding-stage converter 10, the preceding-stage converter 10 adjusts the value of the first voltage V1 according to the feedback signal FB. The adjustment signal DAC_ADJ is converted by the voltage reference and feedback loop 60 to generate a feedback signal FB, and send the feedback signal FB to the preceding-stage converter 10, and the preceding-stage converter 10 can adjust the value of the first voltage V1 according to the feedback signal FB.
In some embodiments, the voltage reference and feedback loop 60 includes a reference voltage chip U2 and an optocoupler U3. The reference voltage chip U2 has a third pin as a ground pin, which is coupled with a signal ground SGND; the reference voltage chip U2 has a second pin as a power supply pin, which is coupled with the preceding-stage converter 10 via a sixteenth resistor R16 and a seventeenth resistor R17 connected in series, and receives the first voltage V1; the reference voltage chip U2 has a first pin as an adjustment pin, which is coupled with the main control module 50 via a twenty-third resistor R23, and receives the adjustment signal DAC_ADJ, the first pin of the reference voltage chip U2 is also coupled with the signal ground SGND via a twentieth resistor R20, is also coupled with the preceding-stage converter 10 via an eighteenth resistor R18, and is also coupled with the second pin of the reference voltage chip U2 via an eighth capacitor C8 and a twenty-first resistor R21 which are connected in series; the optocoupler U3 has a first pin and a second pin, which are connected in parallel with both ends of the seventeenth resistor R17. The optocoupler has a third pin, which is coupled with a power ground PGND. The optocoupler U3 has a fourth pin, which is coupled with the preceding-stage converter 10, outputs a feedback signal FB, and sends the feedback signal FB to the preceding-stage converter 10. In a specific embodiment, the model of the reference voltage chip U2 is TL431M. The adjustment signal DAC_ADJ, which is as an analog signal, is converted via the voltage reference and feedback loop 60 to generate the feedback signal FB, which can be used to control the preceding-stage converter 10 to change the first voltage V1 output.
In some embodiments, the preceding-stage converter 10 includes an auxiliary control chip U1, a power transistor Q1 and a transformer T1. The auxiliary control chip U1 has an eighth pin as a feedback pin, which is coupled with the voltage reference and feedback loop 60, and receives a feedback signal FB provided by the voltage reference and feedback loop 60. The eighth pin of the auxiliary control chip U1 is also coupled with the power ground PGND via a third capacitor C3; the auxiliary control chip U1 has a second pin as a power pin, which is coupled with the transformer T1 via a sixth resistor D6 and a third diode D3 connected in series, and is also coupled with the power ground PGND via a third electrolytic capacitor EC3; the auxiliary control chip U1 has a seventh pin as a ground pin, which is coupled with the power ground PGND; the auxiliary control chip U1 has a fifth pin as a control pin, which is coupled with the transformer T1 via the power transistor Q1. In a specific embodiment, the model of the auxiliary control chip U1 is HFC0100HS. According to the difference in the feedback signal FB, the value of the first voltage V1 output can be adjusted.
More specifically, in some embodiments, the preceding-stage converter 10 further includes a rectifier bridge DB1, and an input end of the rectifier bridge DB1 is coupled with the external power supply. In a specific embodiment, the external power supply is AC power, and both ends of the input end of the rectifier bridge DB1 are coupled with the AC power via a live wire L and a neutral wire N respectively. A first electrolytic capacitor EC1 is connected in parallel between two of output ends of the rectifier bridge DB1, and one of the two of output ends of the rectifier bridge (DB1) is then coupled with the transformer T1. The transformer T1 has a first pin, a third pin, a fifth pin, a sixth pin, a ninth pin, and a tenth pin. A primary winding of the transformer T1 is provided between the first pin and the third pin of the transformer T1. A secondary winding of the transformer T1 is provided between the ninth pin and the tenth pin of transformer T1, and an auxiliary winding of transformer T1 is provided between the fifth pin and the sixth pin of the transformer T1. The first pin of the transformer T1 is coupled with the first end of the output end of the rectifier bridge DB1, the second end of the output end of the rectifier bridge DB1 is coupled with the power ground PGND, and the third pin of the transformer T1 is coupled with the drain electrode of the power transistor Q1. A fourth diode D4 and a fourth electrolytic capacitor EC4 are connected in series between the ninth pin and the tenth pin of the transformer T1, and the tenth pin of the transformer T1 is coupled with the signal ground SGND, and the coupling point of the fourth diode D4 and the fourth electrolytic capacitor EC4 outputs the first voltage V1. The fifth pin of the transformer T1 is coupled with the power ground PGND, and the sixth pin of the transformer T1 is coupled with the second pin of the auxiliary control chip U1 through the third diode D3 and the sixth resistor D6 which are connected in series. The auxiliary control chip U1 further has a first pin as a valley detection pin, which is coupled with the sixth pin of the transformer T1 via a seventh resistor R7, and is coupled with the power ground PGND via a fifth capacitor C5. The auxiliary control chip U1 further has a fourth pin as a voltage and power supply pin HV, which is coupled with the first end of the output end of the rectifier bridge DB1 via a fifth resistor R5. The auxiliary control chip U1 further has a sixth pin as a sampling pin CS, which is coupled with the power ground PGND via a fourth capacitor C4, coupled with the power ground PGND via the twelfth resistor R12, and coupled with the source electrode of the transistor Q1. The fifth pin of the auxiliary control chip U1 is coupled with the gate electrode of the power transistor Q1. In this way, the preceding-stage converter 10 can work more completely and safely, adjust the value of the output first voltage V1 according to the difference in the feedback signal FB, and can perform various sampling and detection of the circuit, so as to make the circuit work safely and stably.
In some embodiments, the dimming driving module 20 includes a dimming chip U6, the dimming chip U6 has a second pin as a dimming signal input pin and is coupled with the signal ground SGND via a second resistor R2; the dimming chip U6 has a third pin as a power pin, which is coupled with the signal ground SGND via the first capacitor C1, is coupled with the preceding-stage converter 10 via the first resistor R1, and receives the first voltage V1; the dimming chip U6 has a fifth pin as a driving pin, which is coupled with the external load 70 via the second inductor T2, and is coupled with the preceding-stage converter 10 via the first diode D1, the anode electrode of the first diode D1 is coupled with the first voltage V1, and the cathode electrode of the first diode D1 is coupled with the fifth pin of the dimming chip U6; the dimming chip U6 has a seventh pin as a ground pin, which is coupled with the signal ground SGND. The dimming signal is provided by the main control module 50. The main control chip U5 has a seventh pin as a dimming signal output pin, which is coupled with the dimming driving module 20, and outputs a dimming signal to the dimming driving module 20. That is, the second pin of the dimming chip U6 is coupled with the seventh pin of the main control chip U5, and receives the dimming signal output by the seventh pin of the main control chip U5. In some embodiments, the dimming signal is a PWM signal, that is, the dimming driving module 20 is a PWM chopper dimming driving circuit. More specifically, the dimming chip U6 has an eighth pin as a ground pin, which is coupled with the seventh pin of the dimming chip U6; the dimming chip U6 has a sixth pin, which is also a driving pin, and is coupled with the fifth pin of the dimming chip U6; the dimming chip U6 has a first pin, which is also a voltage stabilization pin LD, and is coupled with the third pin of the dimming chip U6.
In some embodiments, the first detection circuit 30 includes a ninth resistor R9 and an eleventh resistor R11 which are connected in series, a free end of the ninth resistor R9 is coupled with the preceding-stage converter 10 and receives the first voltage V1, a free end of the eleventh resistor R11 is coupled with the signal ground SGND, a the coupling point of the ninth resistor R9 and the eleventh resistor R11 outputs the first detection signal ADC_V1. The second detection circuit 40 includes a fourth resistor R4 and a tenth resistor R10 connected in series, a free end of the fourth resistor R4 is coupled with the dimming driving module 20 and receives the second voltage V2, and a free end of the tenth resistor R10 is coupled with the signal ground SGND, and a coupling point of the fourth resistor R4 and the tenth resistor R10 outputs the second detection signal ADC_V2.
Finally, it should be supplemented that the first pin of the main control chip U5 is coupled with the preceding-stage converter 10 via the voltage conversion chip U4, and converts the first voltage V1 output by the preceding-stage converter 10 to a working voltage required by the main control chip U5. For example, in response to that the first voltage V1 is 24V, the working voltage required by the main control chip U5 is 5V, and the conversion is completed by the voltage conversion chip U4.
The technical solution of the present application has the following beneficial effects:
The dimmable driving circuit of the embodiment of the present application obtains the first voltage output by the preceding-stage converter (that is, the input voltage of the dimming driving module) and the second voltage output by the dimming driving module (that is, the input voltage of the dimming driving module, or the load voltage). According to different load voltages (such as different external loads, that is, the second voltage) and the preset value of the ratio of the second voltage to the first voltage (the highest value of the duty ratio of the dimming driving module), the value of the first voltage output by the preceding-stage converter is adjusted so that the ratio of the second voltage to the first voltage is maintained at the preset value, thereby reducing the discharge period of the inductor in the dimming driving module, and also minimizing the chance that the change of the dimming signal falls within the discharge period of the inductor, thereby reducing the pause in the dimming process and improving the user experience.
The above are only specific implementation modes of the present application, but the protection scope of the present application is not limited thereto. Any change or replacement that can be easily thought of by a person familiar with the technical field within the technical scope disclosed in the present application should be covered by the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the appended claims. In addition, specific examples are used in the specification to illustrate the principles and implementation modes of the present application, the descriptions of the above embodiments are only used to help understand the method and core ideas of the present application, and the content of this specification should not be construed as limiting the present application.

Claims

A dimmable driving circuit, comprising:
a preceding-stage converter (10), coupled with an external power supply and configured to output a first voltage (V1);

a dimming driving module (20), coupled with both the preceding-stage converter (10) and an external load (70), and configured to receive the first voltage (V1), output a second voltage (V2), and drive the external load (70) to work;

a first detection circuit (30), coupled with the preceding-stage converter (10), configured to receive the first voltage (V1) and output a first detection signal (ADC_V1) representing the first voltage (V1);

a second detection circuit (40), coupled with the dimming driving module (20), configured to receive the second voltage (V2) and output a second detection signal (ADC_V2) representing the second voltage (V2); and

a main control module (50), coupled with the first detection circuit (30), the second detection circuit (40), and the preceding-stage converter (10), and configured to receive the first detection signal (ADC_V1) and the second detection signal (ADC_V2), output an adjustment signal (DAC_ADJ), and send the adjustment signal (DAC_ADJ) to the preceding-stage converter (10), wherein the preceding-stage converter (10) adjusts a value of the first voltage (V1), a ratio of the second voltage (V2) to the first voltage (V1) is maintained at a preset value.
The dimmable driving circuit according to claim 1, wherein the dimmable driving circuit further comprises a voltage reference and feedback loop (60), the voltage reference and feedback loop (60) is coupled with both the main control module (50) and the preceding-stage converter (10), is configured to receive the adjustment signal (DAC_ADJ) output by the main control module (50), generate a feedback signal (FB) and send the feedback signal (FB) to the preceding-stage converter (10), the preceding-stage converter (10) adjusts the value of the first voltage (V1) according to the feedback signal (FB).
The dimmable driving circuit of claim 1, wherein the main control module (50) comprises a main control chip (U5), the main control chip (U5) comprises a first pin as a power supply pin coupled with an working power supply; the main control chip (U5) comprises a second pin as a first detection pin (CS/PA7) coupled with the first detection circuit (30) and configured to receive the first detection signal (ADC_V1) output by the first detection circuit (30); the main control chip (U5) comprises a third pin as a second detection pin (TKS/PA6) coupled with the second detection circuit (40) and configured to receive the second detection signal (ADC_V2) output by the second detection circuit (40); the main control chip (U5) comprises a third pin as an adjustment signal output pin (RSTB/PA5), configured to output the adjustment signal (DAC_ADJ); the main control chip (U5) comprises an eighth pin as a ground pin coupled with a signal ground (SGND).
The dimmable driving circuit according to claim 3, wherein the main control chip (U5) comprises a seventh pin as a dimming signal output pin, coupled with the dimming driving module (20), and configured to output a dimming signal to the dimming driving module (20).
The dimmable driving circuit according to claim 3, wherein the first pin of the main control chip (U5) is coupled with the preceding-stage converter (10) via a voltage conversion chip (U4).
The dimmable driving circuit according to claim 4, wherein the dimming driving module (20) comprises a dimming chip (U6), comprising a second pin as a dimming signal input pin, and coupled with the signal ground (SGND) via a second resistor (R2); the dimming chip (U6) comprises a third pin as a power supply pin, coupled with the signal ground (SGND) via a first capacitor (C1), coupled with the preceding-stage converter (10) via a first resistor (R1), and configured to receive the first voltage (V1); the dimming chip (U6) comprises a fifth pin as a driving pin, coupled with the external load (70) via a second inductor (T2), and coupled with the preceding-stage converter (10) via a first diode (D1), an anode electrode of the first diode (D1) is coupled with the first voltage (V1), a cathode electrode of the first diode (D1) is coupled with the fifth pin of the dimming chip (U6); the dimming chip (U6) comprises a seventh pin as a ground pin, coupled with the signal ground (SGND).
The dimmable driving circuit according to claim 6, wherein the dimming driving module (20) is a PWM chopper dimming driving circuit, and the dimming signal is a PWM signal.
The dimmable driving circuit according to claim 1, wherein the first detection circuit (30) comprises a ninth resistor (R9) and an eleventh resistor (R11) connected in series, a free end of the ninth resistor (R9) is coupled with the preceding-stage converter (10) and configured to receive the first voltage (V1), a free end of the eleventh resistor (R11) is coupled with a signal ground (SGND), a coupling point of the ninth resistor (R9) and the eleventh resistor (R11) is configured to output the first detection signal (ADC_V1); the second detection circuit (40) comprises a fourth resistor (R4) and a tenth resistor (R10) connected in series, a free end of the fourth resistor (R4) is coupled with the dimming driving module (20) and configured to receive the second voltage (V2), a free end of the tenth resistor (R10) is coupled with the signal ground (SGND), a coupling point of the fourth resistor (R4) and the tenth resistor (R10) is configured to output the second detection signal (ADC_V2).
The dimmable driving circuit according to claim 2, wherein the voltage reference and the feedback loop (60) comprise a reference voltage chip (U2) and an optocoupler (U3), the reference voltage chip (U2) comprises a third pin as a ground pin, which is coupled with a signal ground (SGND); the reference voltage chip (U2) comprises a second pin as a power supply pin, which is coupled with the preceding-stage converter (10) via a sixteenth resistor (R16) and a seventeenth resistor (R17) connected in series, and receives the first voltage (V1); the reference voltage chip (U2) comprises a first pin as an adjustment pin, coupled with the main control module (50) via a twenty-third resistor (R23), and configured to receive the adjustment signal (DAC_ADJ), the first pin of the reference voltage chip (U2) is further coupled with the signal ground (SGND) via a twentieth resistor (R20), further coupled with the preceding-stage converter (10) via an eighteenth resistor (R18), and further coupled with a second pin of the reference voltage chip (U2) via an eighth capacitor (C8) and a twenty-first resistor (R21) connected in series; the optocoupler (U3) comprises a first pin and a second pin, connected in parallel with both ends of the seventeenth resistor (R17), the optocoupler (U3) comprises a third pin coupled with a power ground (PGND), the optocoupler (U3) comprises a fourth pin coupled with the preceding-stage converter (10), and configured to output the feedback signal (FB), and send the feedback signal (FB) to the preceding-stage converter (10).
The dimmable driving circuit according to claim 9, wherein the preceding-stage converter (10) comprises an auxiliary control chip (U1), a power transistor (Q1) and a transformer (T1), the auxiliary control chip (U1) comprises an eighth pin as a feedback pin, coupled with the voltage reference and the feedback loop (60), and configured to receive a feedback signal (FB) provided by the voltage reference and feedback loop (60), the eighth pin of the auxiliary control chip (U1) is further coupled with the power ground (PGND) via a third capacitor (C3); the auxiliary control chip (U1) comprises a second pin as a power supply pin, coupled with the transformer (T1) via a sixth resistor (D6) and a third diode (D3) connected in series, and is further coupled with the power ground (PGND) via a third electrolytic capacitor (EC3); the auxiliary control chip (U1) comprises a seventh pin as a ground pin, coupled with the power ground (PGND); the auxiliary control chip (U1) comprises a fifth pin as a control pin, coupled with the transformer (T1) via the power transistor (Q1).
The dimmable driving circuit according to claim 10, wherein the preceding-stage converter (10) further comprises a rectifier bridge (DB1), an input end of the rectifier bridge (DB1) is coupled with the external power supply, and a first electrolytic capacitor (EC1) is connected in parallel between two of output ends of the rectifier bridge (DB1), and one of the two of output ends of the rectifier bridge (DB1) is then coupled with the transformer (T1).
The dimmable driving circuit according to claim 11, wherein the transformer (T1) comprises a first pin and a third pin, the first pin and the third pin of the transformer (T1) is provided with a primary winding of the transformer (T1) therebetween, the first pin of the transformer (T1) is coupled with a first end of the output end of the rectifier bridge (DB1), a second end of the output end of the rectifier bridge (DB1) is coupled with the power ground (PGND), and the third pin of the transformer (T1) is coupled with a drain electrode of the power transistor (Q1).
The dimmable driving circuit according to claim 11, wherein the transformer (T1) further comprises a fifth pin and a sixth pin, the fifth pin and the sixth pin of the transformer (T1) is provided with an auxiliary winding of the transformer (T1) therebetween, the fifth pin of the transformer (T1) is coupled with the power ground (PGND), the sixth pin of the transformer (T1) is coupled with the second pin of the auxiliary control chip (U1) via the third diode (D3) and the sixth resistor (D6) which are connected in series.
The dimmable driving circuit according to claim 11, wherein the transformer (T1) further comprises a ninth pin and a tenth pin, the ninth pin and the tenth pin of the transformer (T1) is provided with a secondary winding of the transformer (T1) therebetween, a fourth diode (D4) and a fourth electrolytic capacitor (EC4) are connected in series between the ninth pin and the tenth pin of the transformer (T1), and the tenth pin of the transformer (T1) is coupled with the signal ground (SGND), and a coupling point of the fourth diode (D4) and the fourth electrolytic capacitor (EC4) outputs the first voltage (V1).
The dimmable driving circuit according to claim 11, wherein the auxiliary control chip (U1) further comprises a sixth pin as a sampling pin (CS), coupled with the power ground (PGND) via a fourth capacitor (C4), coupled with the power ground (PGND) via a twelfth resistor (R12), and coupled with a source electrode of the power transistor (Q1).